Hardware functional obfuscation with ferroelectric active interconnects
Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-
complexity with significant area, energy, and delay penalty. In this paper, we propose an …
complexity with significant area, energy, and delay penalty. In this paper, we propose an …
Experimental demonstration of gate-level logic camouflaging and run-time reconfigurability using ferroelectric FET for hardware security
Outsourcing of integrated circuit (IC) manufacturing and increasing sophistication of IC
reverse engineering techniques have unleashed security threats such as intellectual …
reverse engineering techniques have unleashed security threats such as intellectual …
Threshold-defined logic and interconnect for protection against reverse engineering
Securing the intellectual property (IP) from counterfeiting is an important goal toward
trustworthy computing. Camouflaging of logic gates is a well-known technique to prevent an …
trustworthy computing. Camouflaging of logic gates is a well-known technique to prevent an …