m-of-n codes can be used for carrying data over selftimed on-chip interconnect links. Such
codes can be chosen to have low redundancy, but the costs of encoding/decoding data is …

As the number of transistors on Integrated Circuits grows VLSI systems are becoming
increasingly complex. In all but the highest performance systems, designers are turning to …

In the field of digital integrated circuits asynchronous and especially quasi delay-insensitive
(QDI) designs are known to have a high robustness against process, voltage and …

Communication costs, which have the potential to throttle design performance as scaling
continues, are mathematically modeled and compared for various pipeline methodologies …

This paper introduces a new family of error-correction unordered (ECU) codes for global
communication, called Zero-Sum. They combine the timing-robustness of delay-insensitive …

Asynchronous controllers exhibit various characteristics that limit the effectiveness and
applicability of the concurrent error detection (CED) methods developed for their …

In this paper a cost effective solution for asynchronous delay-insensitive on-chip
communication is proposed. Our solution is based on the Berger coding scheme and allows …

A majority of the present-day digital systems are clock based or synchronous, which assume
that signals are binary and time is discrete. In general, synchronous systems comprise a …

Parameterized first-order models for throughput, energy, and bandwidth are presented in
this paper. Models are developed for many common pipeline methodologies, including …

A lot of papers have been written on error correcting/detecting codes for data transmission,
but none of the codes are designed to address error correction for delay-insensitive or semi …