Distributed arithmetic architectures for fir filters-a comparative review

G NagaJyothi, S SriDevi - 2017 International conference on …, 2017 - ieeexplore.ieee.org
Finite impulse response (FIR) filter is an influential block in various signal processing
applications. The complexities in VLSI implementation of FIR filters is dominated by the …

A review: FIR filter implementation

MB Trimale - 2017 2nd IEEE International Conference on …, 2017 - ieeexplore.ieee.org
Finite Impulse Response Filter (FIR) has a finite period of the impulse response. Higher
order of FIR filter is required for meeting precise frequency specification in several digital …

A high-performance FIR filter architecture for fixed and reconfigurable applications

BK Mohanty, PK Meher - IEEE transactions on very large scale …, 2015 - ieeexplore.ieee.org
Transpose form finite-impulse response (FIR) filters are inherently pipelined and support
multiple constant multiplications (MCM) technique that results in significant saving of …

A high-performance and energy-efficient FIR adaptive filter using approximate distributed arithmetic circuits

H Jiang, L Liu, PP Jonker, DG Elliott… - … on Circuits and …, 2018 - ieeexplore.ieee.org
In this paper, a fixed-point finite impulse response adaptive filter is proposed using
approximate distributed arithmetic (DA) circuits. In this design, the radix-8 Booth algorithm is …

A blockchain-based traceable IP copyright protection algorithm

L Xiao, W Huang, Y Xie, W Xiao, KC Li - IEEE Access, 2020 - ieeexplore.ieee.org
Current Intellectual Property (IP) copyright protection technologies have low efficiency of
authority management, traceability, and scalability. In this work, a blockchain-based IP …

Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising

M Sumalatha, PV Naganjaneyulu, KS Prasad - Microprocessors and …, 2019 - Elsevier
Abstract In recent years, Finite Impulse Response (FIR) filter plays a major role in signal
processing applications. Earlier many research papers are described the different types of …

High performance hardware design of compressor adder in DA based FIR filters for hearing aids

SR Rammohan, N Jayashri, MA Bivi, CK Nayak… - International Journal of …, 2020 - Springer
Hearing aid is an acoustic device which is worn by hearing loss people. To compensate the
different types of hearing loss, it is necessary to selectively amplify sounds at required …

A resource-efficient multiplierless systolic array architecture for convolutions in deep networks

Y Parmar, K Sridharan - … transactions on circuits and systems II …, 2019 - ieeexplore.ieee.org
This brief presents a resource-efficient VLSI architecture for convolution operations in deep
networks. Taking advantage of a feature of the max pooling layer in classical convolutional …

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic

BK Mohanty, PK Meher, SK Singhal, MNS Swamy - Integration, 2016 - Elsevier
In this paper, we have analyzed the register complexity of direct-form and transpose-form
structures of FIR filter and explored the possibility of register reuse. We find that direct-form …

Partial product addition in Vedic design-ripple carry adder design fir filter architecture for electro cardiogram (ECG) signal de-noising application

TV Padmavathy, S Saravanan… - Microprocessors and …, 2020 - Elsevier
Abstract Design of adder plays a major role in deciding overall performance of system as it is
a major building block through generations of design in an innovative design of circuits. In …