CMOS reliability from past to future: A survey of requirements, trends, and prediction methods

I Hill, P Chanawala, R Singh… - … on Device and …, 2021 - ieeexplore.ieee.org
Developments in IC fabrication, emerging high-reliability markets, and government
regulations indicate potential for significant shifts in how reliability fits within IC development …

Unified quantum and reliability model for ultra-thin double-gate MOSFETs

RY ElKashlan, O Samy, A Anis, Y Ismail, H Abdelhamid - Silicon, 2020 - Springer
This paper presents a unified two-dimensional (2D) threshold voltage model for lightly
doped symmetrical double-gate p-channel MOSFETs including quantum confinement effects …

[PDF][PDF] Double-gate MOSFET model implemented in verilog-AMS language for the transient simulation and the configuration of ultra low-power analog circuits

B Smaani, Y Meraihi, F Nafa… - … of Electronics and …, 2021 - bibliotekanauki.pl
This paper deals with the implementation of a DC and AC double-gate MOSFET compact
model in the Verilog-AMS language for the transient simulation and the configuration of ultra …

Novel Critical Gate-Based Circuit Path-Level NBTI-Aware Aging Circuit Degradation Prediction

H Xu, R Zhu, X Sun, X Fang, P Qi, H Liang… - Journal of Circuits …, 2023 - World Scientific
With the rapid development of semiconductor technology, chip integration is getting beyond
imagination. Aging has become one of the main threats to circuit reliability. In order to …

3D Analytical modeling of potential, drain current, and threshold characteristics for long-channel square gate-all-around (SGAA) MOSFETs

H Abdelhamid, AM Anis, ME Aboulwafa… - Recent Advances in …, 2020 - Springer
Abstract Gate-all-around (GAA)-based field effect transistors (FETs) are considered to be
one of the dominant structures that overcome the performance degradation problems that …

[PDF][PDF] Analysis of the gate-to-channel capacitance variation for the tri-gate nanowire junctionless transistors

B Smaani, Y Yakhelef, F Nafa… - … Global Conference on …, 2021 - researchgate.net
In this paper, the gate-to-channel capacitance variation for the tri-gate nanowire junctionless
transistor (JLT) has been analyzed. It is based on the 2-D electrostatic numerical simulation …

A unified analytical reliability model of NBTI and HCD for undoped double gate PMOS

O Samy, H Abd Elhamid, Y Ismail - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
This paper presents a simple analytical reliability model for potential and threshold voltage
when negative bias temperature instability (NBTI) and hot carrier degradation (HCD) are …

Two dimensional quantum and reliability modelling for lightly doped nanoscale devices

R ElKashlan - 2018 - fount.aucegypt.edu
The downscaling of MOSFET devices leads to well-studied short channel effects and more
complex quantum mechanical effects. Both quantum and short channel effects not only alter …