Optimizing resource efficiencies for scalable full-stack quantum computers

M Fellous-Asiani, JH Chai, Y Thonnart, HK Ng… - PRX Quantum, 2023 - APS
In the race to build scalable quantum computers, minimizing the resource consumption of
their full stack to achieve a target performance becomes crucial. It mandates a synergy of …

64-GHz datapath demonstration for bit-parallel SFQ microprocessors based on a gate-level-pipeline structure

R Kashima, I Nagaoka, M Tanaka… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
We successfully demonstrated an 8-bit-wide, bit-parallel datapath composed of an arithmetic
logic unit and register files for high-throughput oriented SFQ microprocessors based on a …

Superconductive Electronics: A 25-Year Review [Feature]

R Bairamkulov, G De Micheli - IEEE Circuits and Systems …, 2024 - ieeexplore.ieee.org
The challenges of conventional semiconducting electronics, such as dark silicon, memory
wall, and stagnant clock frequency motivate the search for alternative computing …

Rapid single-flux-quantum logic circuits using clockless gates

T Kawaguchi, K Takagi, N Takagi - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
An architecture of rapid single-flux-quantum logic circuits using clockless gates is proposed.
Compared with a circuit composed of only clocked gates, a circuit using clockless gates …

Demonstration of an energy-efficient, gate-level-pipelined 100 TOPS/W arithmetic logic unit based on low-voltage rapid single-flux-quantum logic

I Nagaoka, M Tanaka, K Sano… - 2019 IEEE …, 2019 - ieeexplore.ieee.org
We report the successful operation of an energy-efficient 8-bit arithmetic logic unit (ALU)
based on bit-parallel, gate-Ievel-pipelining, and low-voltage rapid single-flux-quantum (LV …

50-GFLOPS floating-point adder and multiplier using gate-level-pipelined single-flux-quantum logic with frequency-increased clock distribution

I Nagaoka, R Kashima, M Tanaka… - IEEE Transactions …, 2023 - ieeexplore.ieee.org
We demonstrate the functioning of a high-throughput, gate-level-pipelined floating-point
adder and multiplier over 50 GHz. The gate-level-pipelined floating-point adder and …

Demonstration of a 52-GHz bit-parallel multiplier using low-voltage rapid single-flux-quantum logic

I Nagaoka, K Ishida, M Tanaka, K Sano… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
A high-throughput 4 4-bit multiplier was demonstrated using an extremely careful timing
design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the …

Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File

R Kashima, I Nagaoka, T Nakano… - IEEE Transactions …, 2023 - ieeexplore.ieee.org
In this paper, we successfully demonstrate the 50-GHz operation of a microprocessor
datapath based on single-flux-quantum (SFQ) logic with a gate-level pipeline (GLP) …

Cryogenic electronics and quantum information processing

DS Holmes - 2021 IEEE International Roadmap for Devices …, 2021 - ieeexplore.ieee.org
The goal of this International Roadmap for Devices and Systems (IRDS) chapter is to survey,
catalog, and assess the status of technologies in the areas of cryogenic electronics and …

[HTML][HTML] Construction and electrical control of ultrahigh-density organic memory arrays at cryogenic temperature

M Zhong, J Li, Y Zhang, X Li, Z Xu, Q Shen, X Zhang… - Chip, 2023 - Elsevier
Investigation into the structural and magnetic properties of organic molecules at cryogenic
temperature is beneficial for reducing molecular vibration and stabilizing magnetization, and …