Scalable storage and retrieval of multiple asynchronous signals

R Pichumani, C Bunting - US Patent 8,005,992, 2011 - Google Patents
THIRD PARTY MEASUREMENT AND ANALYSIS TOOLS signals having identical time
values within a partition time interval and where at least one additional partition is formed …

System having in-memory buffer service, temporary events file storage system and backup events file uploader service

A Pradeep, A Torman, A Warshavsky, S Jain - US Patent 9,658,801, 2017 - Google Patents
(*) Notice: Subject to any disclaimer, the term of this 5,715.450 A 2f1998 Ambrose et al.
patent is extended or adjusted under 35(Continued) USC 154 (b) by 0 days. Primary …

Partitioning in post-layout circuit simulation

N Zhu - US Patent 11,308,253, 2022 - Google Patents
The independent claims of this patent signify a concise description of embodiments. New
techniques for the parti tioning of big element blocks in a circuit are disclosed. The …

Method and apparatus for substrate noise aware floor planning for integrated circuit design

W Kao, X Dong - US Patent 7,865,850, 2011 - Google Patents
7,024,652 B1 4/2006 McGaughy et al. A methodology is provided to perform noise analysis
in the 7,047,510 B1 52006 Chopra et al. implementation stage of the design of an integrated …

Electrical isomorphism

BW Mcgaughy, WCW Au, B Yang - US Patent 7,373,289, 2008 - Google Patents
Method and system for determining electrical isomorphism between two electrical networks
are disclosed. In one embodiment, the method includes representing the circuit as a …

Efficient isomorphism based simulation of modular multilevel converters

D del Giudice, F Bizzarri, D Linaro… - 2019 IEEE Milan …, 2019 - ieeexplore.ieee.org
Modular multilevel converters (MMCs) are increasingly acquiring a prominent role in modern
high-voltage direct current power systems. Despite the conceptually simple structure of each …

Automated method for buffering in a VLSI design

F Malgioglio, AR Jatkowski, BA Lasseter… - US Patent …, 2011 - Google Patents
Buffers are placed on selected nets coupled to input and output pins of entities in an IC
device. This includes loading selected input and output pins of entities prior to respectively …

Integrated circuit design systems and methods

V Dai, EKC Teoh, J Xu, B Rangarajan - US Patent 10,339,254, 2019 - Google Patents
Methods for integrated circuit design are provided. In one embodiment, a method for
determining a physical layout pattern includes accessing a layout pattern configuration …

Logic circuit model conversion apparatus and method thereof; and logic circuit model conversion program

T Otsuki, N Nonogaki - US Patent 7,822,591, 2010 - Google Patents
A logic circuit model conversion apparatus includes a first analysis unit which analyzes a
model in which a logic circuit of a register transfer level has been coded and outputs …

Statistical circuit simulation

B McGaughy - US Patent 9,031,825, 2015 - Google Patents
Method and system are disclosed for statistical circuit simulation. In one embodiment, a
computer implemented method for statistical circuit simulation includes providing …