A multi-port memory device includes a plurality ports, a plurality of banks, a plurality of global
data buses, first and second I/O controllers, and a test input/output (I/O) controller. The ports …

A write driver circuit includes a write control unit and a write driver. The write control unit is
configured to generate a write control current according to data to be stored. The write driver …

A multiport latch-based memory device includes a latch array, a plurality of first multiplexers,
and a second multiplexer. The latch array is responsive to output data from an input data …

(57) ABSTRACT A semiconductor device also includes programmable termi nation
components and a calibration circuit. The calibration circuit generates impedance calibration …

US7583557B2 - Multi-port memory device with serial input/output interface and control
method thereof - Google Patents US7583557B2 - Multi-port memory device with serial input/output …

An integrated circuit is described that has a substrate with a memory array with dedicated
Support hardware formed on the Substrate. An access wrapper circuit is coupled to address …

Embodiments include a pulsed decision feedback equalization (DFE) circuit. The DFE circuit
may include a current integrating summer (CIS) circuit that passes one or more data signals …

A semiconductor system includes a slave and a master, wherein the slave includes a
plurality of unit memory regions, and is configured to transmit determination result data …

(57) ABSTRACT A semiconductor system includes a slave including a plu rality of unit
memory regions. The semiconductor system further includes a master configured to perform …

Various exemplary embodiments are directed to a semi conductor device in which crosstalk
is minimized when inputting/outputting data, a semiconductor System including the …