Towards fault simulation at mixed register-transfer/gate-level models

E Kaja, N Gerlin, M Vaddeboina, L Rivas… - … on Defect and Fault …, 2021 - ieeexplore.ieee.org
Safety-critical designs used in automotive applications need to ensure reliable operations
even under hostile operating conditions. As these designs grow in size and complexity, they …

[图书][B] Industrial applications of evolutionary algorithms

E Sanchez, G Squillero, A Tonda - 2012 - Springer
The increasing complexity of products and processes leads directly to the growing intricacy
of the problems and issues the industrial world is facing. More and more often, traditional …

Effective techniques for high-level ATPG

F Corno, G Cumani, MS Reorda… - Proceedings 10th Asian …, 2001 - ieeexplore.ieee.org
The ASIC design flow is rapidly moving towards higher description levels, and most design
activities are now performed at the RT-level. However, test-related activities are lacking …

Automation of test program synthesis for processor post-silicon validation

VM Suryasarman, S Biswas, A Sahu - Journal of Electronic Testing, 2018 - Springer
Software-based self-testing (SBST) is introduced for at-speed testing of processors, which is
difficult with any of the external testing techniques. Evolutionary approaches are used for the …

Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG?

A Fin, F Fummi - Eighth IEEE International High-Level Design …, 2003 - ieeexplore.ieee.org
The paper examines the potentialities of genetic algorithms (GAs) with respect to the
development of high-level TPGs. It summarizes at first the most relevant test pattern …

BFS-DEVS: A general DEVS-based formalism for behavioral fault simulation

L Capocchi, F Bernardi, D Federici… - … Modelling Practice and …, 2006 - Elsevier
Discrete event modeling allows designing an easy-to-handle and reusable representation of
a system but, in its classical form, only permits one simulation at a time for a system …

High-level implementation-independent functional software-based self-test for RISC processors

AS Oyeniran, R Ubar, M Jenihhin, J Raik - Journal of Electronic Testing, 2020 - Springer
The paper proposes a novel high-level approach for implementation-independent
generation of functional software-based self test programs for processors with RISC …

An automated methodology for cogeneration of test blocks for peripheral cores

L Bolzani, E Sánchez, M Schillaci… - … International On-Line …, 2007 - ieeexplore.ieee.org
Test of peripheral modules has not yet been deeply investigated by the research community.
When embedded in a system on a chip, peripheral cores introduce new issues for post …

RTL fault modeling

M Karunaratne, A Sagahayroon… - … Midwest Symposium on …, 2005 - ieeexplore.ieee.org
Testing of digital circuits has traditionally been done using fault models at the gate level or
below. Use of these lower level fault models adds complexity and delays testing efforts to …

Enhancing health-care services with mixed reality systems

V Stantchev - The Engineering of Mixed Reality Systems, 2010 - Springer
This work presents a development approach for mixed reality systems in health care.
Although health-care service costs account for 5–15% of GDP in developed countries the …