Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies
W Kim, JD Hopkins, C Kim - US Patent 10,790,303, 2020 - Google Patents
Some embodiments include a memory array having a vertical stack of alternating insulative
levels and wordline levels. The wordline levels include conductive wordline material having …
levels and wordline levels. The wordline levels include conductive wordline material having …
Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies
BC Kim, FH Fabreguette, RJ Hill, P Narayanan… - US Patent …, 2021 - Google Patents
Some embodiments include a memory array having a vertical stack of alternating insulative
levels and wordline levels. The wordline levels have conductive terminal ends within control …
levels and wordline levels. The wordline levels have conductive terminal ends within control …
Semiconductor structure with diffusion break and method
MJH Van Dal, T Vasen, G Doornbos - US Patent 11,276,832, 2022 - Google Patents
The current disclosure describes techniques for forming semiconductor structures having
multiple semiconductor strips configured as channel portions. In the semiconductor …
multiple semiconductor strips configured as channel portions. In the semiconductor …
Semiconductor storage device
M Yamaoka, K Tomishige, N Yamamoto - US Patent 11,658,155, 2023 - Google Patents
(57) ABSTRACT A semiconductor storage device includes a substrate, a plurality of
conductive layers arranged in a first direction intersecting a surface of the substrate, and a …
conductive layers arranged in a first direction intersecting a surface of the substrate, and a …
Memory device including mixed oxide charge trapping materials and methods for forming the same
RNB Said, S Kanakamedala, RS Makala… - US Patent …, 2024 - Google Patents
A memory device includes an alternating stack of insulating layers and electrically
conductive layers located over a substrate, a memory opening fill structure including a …
conductive layers located over a substrate, a memory opening fill structure including a …
Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies
BC Kim, FH Fabreguette, RJ Hill, P Narayanan… - US Patent …, 2024 - Google Patents
Some embodiments include a memory array having a vertical stack of alternating insulative
levels and wordline levels. The wordline levels have conductive terminal ends within control …
levels and wordline levels. The wordline levels have conductive terminal ends within control …
Gate all around semiconductor structure with diffusion break
MJH Van Dal, T Vasen, G Doornbos - US Patent 12,089,423, 2024 - Google Patents
The current disclosure describes techniques for forming semiconductor structures having
multiple semiconductor strips configured as channel portions. In the semiconductor …
multiple semiconductor strips configured as channel portions. In the semiconductor …
Memory devices including different tier pitches, and related electronic systems
Y Liu, T Ghilardi, G Matamis… - US Patent App. 18 …, 2023 - Google Patents
H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating
or switching and having potential barriers; Capacitors or resistors having potential barriers …
or switching and having potential barriers; Capacitors or resistors having potential barriers …
Gate all around semiconductor structure with diffusion break
MJH Van Dal, T Vasen, G Doornbos - US Patent 11,653,507, 2023 - Google Patents
The current disclosure describes techniques for forming semiconductor structures having
multiple semiconductor strips configured as channel portions. In the semiconductor …
multiple semiconductor strips configured as channel portions. In the semiconductor …
Microelectronic devices including varying tier pitch, and related electronic systems
Y Liu, T Ghilardi, G Matamis, JD Shepherdson… - US Patent …, 2023 - Google Patents
A microelectronic device comprises a first set of tiers, each tier of the first set of tiers
comprising alternating levels of a conductive material and an insulative material and having …
comprising alternating levels of a conductive material and an insulative material and having …