Electronic devices and systems, and methods for making and using the same

SE Thompson, DR Thummalapally - US Patent 8,273,617, 2012 - Google Patents
(57) ABSTRACT A suite of novel structures and methods is provided to reduce power
consumption in a wide array of electronic devices and systems. Some of these structures …

Low power design for future wearable and implantable devices

K Lundager, B Zeinali, M Tohidi, JK Madsen… - Journal of low power …, 2016 - mdpi.com
With the fast progress in miniaturization of sensors and advances in micromachinery
systems, a gate has been opened to the researchers to develop extremely small …

Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-/spl mu/m MOSFET's with epitaxial and/spl delta/-doped channels

A Asenov, S Saini - IEEE Transactions on Electron Devices, 1999 - ieeexplore.ieee.org
A detailed three-dimensional (3-D) statistical" atomistic" simulation study of fluctuation-
resistant sub 0.1-/spl mu/m MOSFET architectures with epitaxial channels and delta doping …

Process-variation effect, metal-gate work-function fluctuation, and random-dopant fluctuation in emerging CMOS technologies

Y Li, CH Hwang, TY Li, MH Han - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations
consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and …

Transistor with threshold voltage set notch and method of fabrication thereof

R Arghavani, P Ranade, L Shifren… - US Patent …, 2014 - Google Patents
6,808 004 B2 10/2004 Kamm et a1, 7,398,497 B2 7/2008 Sato et 31. 63083994 B1 10/2004
Wang 7,402,207 B1 7/2008 Besser et a1. 6,813,750 B2 11/2004 Usami et 31 ' 7,402,872 B2 …

Electronic devices and systems, and methods for making and using the same

SE Thompson, DR Thummalapally - US Patent 8,604,530, 2013 - Google Patents
Some structures and methods to reduce power consumption in devices can be implemented
largely by reusing existing bulk CMOS process flows and manufacturing technology …

Impact of geometrical parameters and substrate on analog/RF performance of stacked nanosheet field effect transistor

V Jegadheesan, K Sivasankaran, A Konar - Materials Science in …, 2019 - Elsevier
In this paper, the impact of the substrate on the performance of three channels Stacked
Nanosheet Field Effect Transistor (SNSH-FET) is studied, and the Super-Steep-Retrograde …

Low power semiconductor transistor structure and method of fabrication thereof

L Shifren, P Ranade, SE Thompson… - US Patent …, 2013 - Google Patents
Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced
OV, compared to conven tional bulk CMOS and can allow the threshold voltage V of FETs …

Low power and low voltage MOSFETs with variable threshold voltage controlled by back-bias

T Hiramoto, M Takamiya - IEICE Transactions on Electronics, 2000 - search.ieice.org
We have studied the characteristic trade-offs in low power and low voltage MOSFETs from
the viewpoint of back-gate control and body effect factor. Previously reported MOSFET …

Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications

K Fujita, Y Torii, M Hori, J Oh, L Shifren… - 2011 International …, 2011 - ieeexplore.ieee.org
We have achieved aggressive reduction of VT variation and V DD-min by a sophisticated
planar bulk MOSFET named 'Deeply Depleted Channel™(DDC)'. The DDC transistor has …