Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)
Because of its high storage density with superior scalability, low integration cost and
reasonably high access speed, spin-torque transfer random access memory (STT RAM) …
reasonably high access speed, spin-torque transfer random access memory (STT RAM) …
Enabling universal memory by overcoming the contradictory speed and stability nature of phase-change materials
W Wang, D Loke, L Shi, R Zhao, H Yang, LT Law… - Scientific Reports, 2012 - nature.com
The quest for universal memory is driving the rapid development of memories with superior
all-round capabilities in non-volatility, high speed, high endurance and low power. Phase …
all-round capabilities in non-volatility, high speed, high endurance and low power. Phase …
A review paper on memory fault models and test algorithms
Testing embedded memories in a chip can be very challenging due to their high-density
nature and manufactured using very deep submicron (VDSM) technologies. In this review …
nature and manufactured using very deep submicron (VDSM) technologies. In this review …
Advances of embedded resistive random access memory in industrial manufacturing and its potential applications
Z Wang, Y Song, G Zhang, Q Luo, K Xu… - … Journal of Extreme …, 2024 - iopscience.iop.org
Embedded memory, which heavily relies on the manufacturing process, has been widely
adopted in various industrial applications. As the field of embedded memory continues to …
adopted in various industrial applications. As the field of embedded memory continues to …
Single- and Multiple-Event Induced Upsets in 1T1R RRAM
WG Bennett, NC Hooten, RD Schrimpf… - … on Nuclear Science, 2014 - ieeexplore.ieee.org
Single-event upsets in 1T1R Resistive Random Access Memory (RRAM) structures are
experimentally demonstrated by generating current transients in the access transistors of the …
experimentally demonstrated by generating current transients in the access transistors of the …
Optimizing SRAM bitcell reliability and energy for IoT applications
This paper compares six different 8T SRAM bitcells targeting different design space
requirements-such as reliability and low power/energy-for Internet of Things (IoT) …
requirements-such as reliability and low power/energy-for Internet of Things (IoT) …
Compositional system-level design exploration with planning of high-level synthesis
HY Liu, M Petracca, LP Carloni - 2012 Design, Automation & …, 2012 - ieeexplore.ieee.org
The growing complexity of System-on-Chip (SoC) design calls for an increased usage of
transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed …
transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed …
Supporting distributed shared memory on multi-core network-on-chips using a dual microcoded controller
Supporting Distributed Shared Memory (DSM) is essential for multi-core Network-on-Chips
for the sake of reusing huge amount of legacy code and easy programmability. We propose …
for the sake of reusing huge amount of legacy code and easy programmability. We propose …
Trend and challenge on system-on-a-chip designs
The success of system-on-a-chip (SoC) hinges upon a well-concerted integrated approach
from multiple disciplines, such as device, design, and application. From the device …
from multiple disciplines, such as device, design, and application. From the device …
Design techniques to improve the device write margin for MRAM-based cache memory
As one promising non-volatile memory technology, magnetoresistive RAM (MRAM) based
on magnetic tunneling junctions (MTJs) has recently attracted much attention. However …
on magnetic tunneling junctions (MTJs) has recently attracted much attention. However …