Ultra-precision thinning technology using workpiece self-rotational grinding followed by
chemical mechanical polishing (CMP) is extensively applied in the integrated circuit …

To address the debate surrounding the stress criterion for a-Si transformation during the
scratching process caused by the particular grain, atomic-scale single grain scratching MD …

To address the problem of low polishing efficiency in traditional loose-abrasive chemical
mechanical polishing, a humidity-controlled fixed-abrasive chemical mechanical polishing …

Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW)
for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects …

Silicon carbide (SiC) is a promising semiconductor material which attracts huge attention
due to its wide bandgap, high thermal conductivity and great potential for electronic …

Three-dimensional integration using through-silicon via (TSV) can significantly improve the
performance and power consumption of microelectronic devices. In order to connect more …

Dispersion nature of surface acoustic waves (SAWs) propagating along the machined
surface contains key information about the elastic properties and stress state of the …

Subsurface damage (SSD) induced by silicon wafer grinding process is an unavoidable
problem in semiconductor manufacturing. Although experimental attempts have been made …

The ultra-precision grinding technology based on a workpiece self-rotational principle is
extensively used for silicon wafer thinning in the chip post-processing. Nevertheless, owing …

The existing stress criterion assumes the material to be isotropic and only distinguishes
elastic, plastic, and crack zones, to explain the scratching-induced sub-surface defects …