Precessional spin current structure for MRAM
MM Pinarbasi, M Tzoufras - US Patent 9,853,206, 2017 - Google Patents
A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a
magnetic tunnel junction stack having a significantly improved performance of the free layer …
magnetic tunnel junction stack having a significantly improved performance of the free layer …
Spin transfer torque structure for MRAM devices having a spin current injection capping layer
BA Kardasz, MM Pinarbasi - US Patent 9,728,712, 2017 - Google Patents
A magnetoresistive random-access memory (MRAM) device is disclosed. The device
described herein has a spin current injection capping layer between the free layer of a …
described herein has a spin current injection capping layer between the free layer of a …
Memory cell having magnetic tunnel junction and thermal stability enhancement layer
M Pinarbasi, B Kardasz - US Patent 9,741,926, 2017 - Google Patents
(57) ABSTRACT A magnetoresistive random-access memory (MRAM) device is disclosed.
The device described herein has a thermal stability enhancement layer over the free layer of …
The device described herein has a thermal stability enhancement layer over the free layer of …
Precessional spin current structure with non-magnetic insertion layer for MRAM
BA Kardasz, MM Pinarbasi - US Patent 10,665,777, 2020 - Google Patents
A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a
magnetic tunnel junction stack having a significantly improved performance of the free layer …
magnetic tunnel junction stack having a significantly improved performance of the free layer …
Precessional spin current structure with high in-plane magnetization for MRAM
MM Pinarbasi, BA Kardasz - US Patent 10,672,976, 2020 - Google Patents
A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a
magnetic tunnel junction stack having a significantly improved performance of the free layer …
magnetic tunnel junction stack having a significantly improved performance of the free layer …
Polishing stop layer (s) for processing arrays of semiconductor elements
MM Pinarbasi, JA Hernandez, A Datta… - US Patent …, 2017 - Google Patents
Described embodiments can be used in semiconductor manufacturing and employ materials
with high and low polish rates to help determine a precise polish end point that is consistent …
with high and low polish rates to help determine a precise polish end point that is consistent …
Method and apparatus for bipolar memory write-verify
N Berger, B Louie, M El-Baraji - US Patent 10,163,479, 2018 - Google Patents
An advantageous write verify operation for bipolar memory devices is disclosed. The verify
operation is performed under the same bias conditions as the write operation. Thus, the …
operation is performed under the same bias conditions as the write operation. Thus, the …
High annealing temperature perpendicular magnetic anisotropy structure for magnetic random access memory
BA Kardasz, MM Pinarbasi, JA Hernandez - US Patent 10,468,590, 2019 - Google Patents
A perpendicular synthetic antiferromagnetic (pSAF) structure and method of making such a
structure is disclosed. The pSAF structure can be a first high perpendicular Magnetic …
structure is disclosed. The pSAF structure can be a first high perpendicular Magnetic …
Shared bit line array architecture for magnetoresistive memory
L Hoang, A Levi - US Patent 10,679,685, 2020 - Google Patents
A magnetoresistive memory architecture in one aspect includes a plurality of bit lines each
coupled to two or more respective columns of magnetoresistive memory cells, and a plurality …
coupled to two or more respective columns of magnetoresistive memory cells, and a plurality …
Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers
N Berger, B Louie, M El-Baraji, L Crudele… - US Patent …, 2019 - Google Patents
A memory pipeline for performing a write operation in a memory device is disclosed. The
memory pipeline comprises an input register operable to receive a first data word and an …
memory pipeline comprises an input register operable to receive a first data word and an …