ASSistant Examiner-Phallaka Kik 57 ABSTRACT A method for refining the position of
linearly aligned cells on the Surface of a Semiconductor chip is disclosed herein. The …

Incremental timing analyzer for selectively performing tim ing analysis on a revised
electronic circuit design resulting from one or more modifications to an initial electronic …

In areas where the arrangement of objects is a primary concern, such as in the
semiconductor chip industry or the architectural industry," manual" layout using computer …

A system for determining an affinity associated with relocating a cell located on a surface of
a semiconductor chip to a different location on the surface is disclosed herein. Each cell may …

54 METHOD OF EXTRACTING LAYOUT Fukuda, Sanae et al., IEEE Transactions on
Comput PARASTICS FOR NETS OF AN er-Aided Design, vol. 9, No. 1, Jan. 1990,“A ULSI 2 …

A method for improving the timing performance of a standard cell ASIC layout. The method is
operable at any phase of the ASIC design cycle including following the completion of layout …

Integrated circuits are electrical circuits comprised of transistors, resistors, capacitors, and
other components on a single semiconductor “chip” in which the components are …

A layout parasitics extraction system. The layout parasitics extraction system is a connectivity-
based approach for extracting layout parasitics. The system creates a connectivity-based …

A method and apparatus to enable the size reduction of geometric databases used in the
analysis of integrated circuit layouts. The results of design rule analysis on the groups of …

An method of creating a physical layout of an integrated circuit. A schematic? le (600) is
mapped directly to a physical layout using the location of elements and routing of …