Energy Efficient ADC Design Techniques
P Harpe - 2024 IEEE Custom Integrated Circuits Conference …, 2024 - ieeexplore.ieee.org
In this review paper, we will have a look at ADC efficiency trends over the years as function
of ADC architecture, resolution, and sampling rate. After that, state-of-the-art design …
of ADC architecture, resolution, and sampling rate. After that, state-of-the-art design …
A new digital background calibration technique for pipeline analog to digital converters using decision points of the voltage transfer characteristics
K Ghanbari, E Farshidi, N Alaei Sheini - Analog Integrated Circuits and …, 2024 - Springer
A new technique is introduced for digital background calibration in pipeline analog to digital
converters (ADCs). The technique is based on the decision points of the voltage transfer …
converters (ADCs). The technique is based on the decision points of the voltage transfer …
[PDF][PDF] Design and Implementation of BIST Architecture for Static Parameter of ADC
A Jangi, M Dixit, MK Ojha - 2024 - ijmit.org
This paper provides a comprehensive analysis of On-Chip ADC BIST and compare it to the
Off-Chip static parameter, which is the non-linearity of SAR ADC. It also evaluates the …
Off-Chip static parameter, which is the non-linearity of SAR ADC. It also evaluates the …
A Novel Hybrid Technique for Static Offset Voltage Calibration in Dynamic Comparators Leveraging Bulk Voltage and Shunt Current Trimming
F Nessir Zghoul, T Mansour, G Latif - Takwa and alghazo, jaafar and … - papers.ssrn.com
In this paper, a new hybrid digitally controlled circuit technique is proposed to calibrate the
static offset voltage in the preamplifier stage for the Strong-Arm latch-based dynamic …
static offset voltage in the preamplifier stage for the Strong-Arm latch-based dynamic …