Photonic network-on-chip (PNoC) architectures employ photonic waveguides with dense-
wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators …

The compact size and high wavelength-selectivity of microring resonators (MRs) enable
photonic networks-on-chip (PNoCs) to utilize dense-wavelength-division-multiplexing …

This paper introduces 3D-ProWiz, which is a high-bandwidth, energy-efficient, optically-
interfaced 3D DRAM architecture with fine grained data organization and activation. 3D …

The compact size and high wavelength selectivity of microring resonators (MRs) enable
photonic networks-on-chip (PNoCs) to utilize dense-wavelength-division-multiplexing …

Photonic network-on-chip (PNoC) architectures employ photonic links with dense
wavelength-division multiplexing (DWDM) to enable high throughput on-chip transfers …

This paper presents a novel, energy-efficient DRAM refresh technique called massed
refresh that simultaneously leverages bank-level and sub array-level concurrency to reduce …

WIDE I/O DRAM is a promising 3-D memory architecture for low-power/highperformance
computing. This paper proposes a new WIDE I/O DRAM architecture to reduce access …

3D stacking improves bandwidth, energy, and latency of DRAMs by exploiting shorter and
more abundant wiring in three dimensions. While future stacks are predicted to provide tens …

This paper presents a high-bandwidth 3D graphics DRAM architecture (3D-SGDRAM) with
reduced access time and energy consumption. A novel 3D bank organization is employed …

In this paper, we proposed a heuristic algorithm for minimizing the critical access time on a
3D data bus based on inserted bus switches and repeaters. Given the topology of a 3D data …