[HTML][HTML] Strain engineering in functional materials
Silicon based complementary metal-oxide-semiconductor field-effect-transistor (CMOSFET)
technology has continued to progress unabated for last five decades despite various …
technology has continued to progress unabated for last five decades despite various …
Method for making a semiconductor device with self-aligned inner spacers
S Reboh, E Augendre, R Coquand - US Patent 10,217,842, 2019 - Google Patents
(57) ABSTRACT A method for making a semiconductor device, including: a) making, on a
substrate, a stack comprising a first semiconductor portion able to form an active zone and …
substrate, a stack comprising a first semiconductor portion able to form an active zone and …
[HTML][HTML] Four-period vertically stacked SiGe/Si channel FinFET fabrication and its electrical characteristics
Y Li, F Zhao, X Cheng, H Liu, Y Zan, J Li, Q Zhang… - Nanomaterials, 2021 - mdpi.com
In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe
channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel …
channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel …
Reduction of MOS Interface Defects in TiN/Y₂O₃/Si₀. ₇₈Ge₀. ₂₂ Structures by Trimethylaluminum Treatment
We report improvement of TiN/Y 2 O 3/Si 0.78 Ge 0.22 metal-oxide-semiconductor (MOS)
interface properties by employing the trimethylaluminum (TMA) pretreatment before Y 2 O 3 …
interface properties by employing the trimethylaluminum (TMA) pretreatment before Y 2 O 3 …
Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed
WE Wang - US Patent 10,770,353, 2020 - Google Patents
US10770353B2 - Method of forming multi-threshold voltage devices using dipole-high dielectric
constant combinations and devices so formed - Google Patents US10770353B2 - Method of …
constant combinations and devices so formed - Google Patents US10770353B2 - Method of …
Enhanced Reliability of Ferroelectric HfZrOx on Semiconductor by Using Epitaxial SiGe as Substrate
KY Chen, YH Huang, RW Kao, YX Lin… - … on Electron Devices, 2019 - ieeexplore.ieee.org
As compared with Si as the substrate, ferroelectric (FE) HfZrO x with orthorhombic phase on
Si 0.56 Ge 0.44 substrate was found to demonstrate improved FE characteristics. Through …
Si 0.56 Ge 0.44 substrate was found to demonstrate improved FE characteristics. Through …
Novel stacked SiGe/Si FinFET device with subthreshold swing of 68 mV/dec using optimized thermal budget and channel passivation technology
F Zhao, Y Li, JY Zhang, X Jia, A Chen, W Wang - Silicon, 2023 - Springer
In this study, the optimized thermal budget and channel passivation technology for a novel
stacked SiGe/Si FinFET are investigated. A vertical stacked SiGe/Si fin with no significantly …
stacked SiGe/Si FinFET are investigated. A vertical stacked SiGe/Si fin with no significantly …
Fabrication and selective wet etching of Si0. 2Ge0. 8/Ge multilayer for Si0. 2Ge0. 8 channel gate-all-around MOSFETs
H Liu, Y Li, X Cheng, Y Zan, Y Lu, G Wang, J Li… - Materials Science in …, 2021 - Elsevier
The fabrication and selective wet etching of Si 0.2 Ge 0.8/Ge stacked multilayer for Si 0.2 Ge
0.8 channel gate-all-around metal–oxide–semiconductor field-effect transistors (MOSFETs) …
0.8 channel gate-all-around metal–oxide–semiconductor field-effect transistors (MOSFETs) …
Low-Temperature-Grown Single-Crystal Si Epitaxially on Ge, Followed by Direct Deposition of High-κ Dielectrics–Attainment of Low Interfacial Traps and Highly …
Single-crystal silicon (Si) of six monolayer thickness was epitaxially grown on epi-
germanium (Ge) in the (001) orientation at substrate temperatures lower than 300° C …
germanium (Ge) in the (001) orientation at substrate temperatures lower than 300° C …
Impact of High-Temperature Annealing on Interfacial Layers Grown by O2 Plasma on Si0.5Ge0.5 Substrates
MC Lee, HR Lin, WL Lee, NJ Chung… - … on Electron Devices, 2022 - ieeexplore.ieee.org
This article demonstrates the influence of high-temperature annealing on an interfacial layer
(IL) grown by O 2 plasma on Si 0.5 Ge 0.5 substrates. The X-ray photoelectron spectroscopy …
(IL) grown by O 2 plasma on Si 0.5 Ge 0.5 substrates. The X-ray photoelectron spectroscopy …