The control synthesis of a dynamic system subject to a signal temporal logic (STL)
specification is commonly formulated as a mixed-integer linear/convex programming …

Reactive synthesis for the GR (1) fragment of LTL has been implemented and studied in
many works. In this work we present and evaluate a list of heuristics to potentially reduce …

Reactive synthesis is used to automatically generate circuits or programs from temporal
logic specifications. In propositional reactive synthesis, generalized reactivity (1)(GR (1)) has …

Reactive synthesis is an automated procedure to obtain a correct-by-construction reactive
system from its temporal logic specification. GR (1) is an expressive assume-guarantee …

Reactive synthesis, where a finite-state system is automatically generated from its
specification, is a particularly ambitious way to engineer correct-by-construction systems. In …

This paper proposes a language for describing reactive synthesis problems that integrates
imperative and declarative elements. The semantics is defined in terms of two-player turn …

Abstract Specification is the first and arguably the most important step for formal verification
and correct-by-construction synthesis. These tasks require understanding precisely a …

Reactive synthesis for the GR (1) fragment of LTL has been implemented and studied in
many works. In this workshop paper we present and evaluate a list of heuristics to potentially …

Concurrency plays a crucial role in today's computing systems. For hardware systems,
pipelining is an important and widespread mechanism to increase throughput. Such …

This report describes a number of changes to the ARM AMBA bus case study from [1] that
lead to significant reduction in synthesis time. In addition, it identifies the reason of blowup …