The mid-rise time-to-digital converter (TDC), eg, a binary (bang-bang) phase detector and
other few-bit TDCs, is commonly used as the phase detector (PD) in a digital phase locked …

A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its
output frequency is not an integer multiple of its reference frequency. Until recently, it …

Digital-to-time converters (DTC's) used in fractional-phase locked loops (PLL's) aim to zero
the quantization error (QE) introduced by the divider controller in order to recover integer …

Phase locked loops for fractional frequency synthesis typically use Digital Modulators
(DDSMs) as their divider controllers. Different types and configurations of DDSMs have been …

Spurious tones appear in the output phase noise spectrum of a fractional-N frequency
synthesizer when nonlinearities are present in the loop. These spurs are generated by the …

Flicker noise and white noise from the charge pump (CP) within a phase locked loop (PLL)
are key contributors to the close‐in phase noise floor of a fractional‐N frequency …

This article presents a frequency synthesizer for generating quadrature local-oscillator (LO)
waveforms covering an octave range of 6 to 12-GHz. It uses two voltage-controlled …

The divider controller in a conventional phase-locked loop fractional-frequency synthesizer
modulates the instantaneous division ratio of the feedback divider. The divider controller is …

Fractional-frequency synthesizers that use a digital–modulator (DDSM) to control the
feedback divider can exhibit spurious tones that move about in the frequency domain; these …

Abstract A Digital-to-Time Converter based (DTC-based) fractional-N digital phase-locked
loop (DPLL) using probability-density-shaping (PDS) spur immunity and quantization phase …