Logic BIST with capture-per-clock hybrid test points

E Moghaddam, N Mukherjee, J Rajski… - … on Computer-Aided …, 2018 - ieeexplore.ieee.org
Logic built-in self-test (LBIST) is now increasingly used with on-chip test compression as a
complementary solution for in-system test, where high quality, low power, low silicon area …

Test time and area optimized BrST scheme for automotive ICs

N Mukherjee, D Tille, M Sapati, Y Liu… - 2019 IEEE …, 2019 - ieeexplore.ieee.org
As cars become increasingly computerized and their safety functions are evolving rapidly,
the number of complex safety-critical components deployed in advanced driver assistance …

Test point insertion for multi-cycle power-on self-test

S Wang, X Zhou, Y Higami, H Takahashi… - ACM Transactions on …, 2023 - dl.acm.org
Under the functional safety standard ISO26262, automotive systems require testing in the
field, such as the power-on self-test (POST). Unlike the production test, the POST requires …

Time and area optimized testing of automotive ICs

N Mukherjee, D Tille, M Sapati, Y Liu… - … Transactions on Very …, 2020 - ieeexplore.ieee.org
As cars become increasingly computerized and their safety functions evolve rapidly, the
number of complex safety-critical components deployed in advanced driver assistance …

Functional Compaction for Functional Test Sequences

I Pomeranz - IEEE Access, 2024 - ieeexplore.ieee.org
The occurrence of silent data corruption because of hardware defects in large scale data
centers points to the advantages of applying functional test sequences to detect hardware …

Full-scan LBIST with capture-per-cycle hybrid test points

S Milewski, N Mukherjee, J Rajski… - 2017 IEEE …, 2017 - ieeexplore.ieee.org
This paper presents a novel low-area scan-based logic built-in self-test (LBIST) scheme that
addresses stringent test requirements of certain application domains such as the fast …

Staggered ATPG with capture-per-cycle observation test points

Y Liu, J Rajski, SM Reddy, J Solecki… - 2018 IEEE 36th VLSI …, 2018 - ieeexplore.ieee.org
This paper presents a new staggered test pattern generation scheme. It produces
deterministic stimuli in the course of a test-per-clock-based process by using dedicated …

Diagnostic test point insertion and test compaction

I Pomeranz - IEEE Transactions on Very Large Scale …, 2022 - ieeexplore.ieee.org
Test points are inserted into a circuit to improve its testability or diagnosability. The
diagnosability goal may be to reduce the number of indistinguished fault pairs, increase the …

Increased detection of hard-to-detect stuck-at faults during scan shift

H Jiang, F Zhang, J Dworak, K Nepal… - Journal of Electronic …, 2023 - Springer
Test sets that target standard fault models may not always be sufficient for detecting all
defects. To evaluate test sets for the detection of unmodeled defects, n-detect test sets …

Automotive functional safety assurance by POST with sequential observation

S Wang, Y Higami, H Takahashi, H Iwata… - IEEE Design & …, 2018 - ieeexplore.ieee.org
Power-on self-test is an efficient means for covering safety-critical faults in automotive
systems. This paper presents a multicycle logic BIST technique that avoids fault masking …