A survey of techniques for designing and managing CPU register file
S Mittal - Concurrency and Computation: Practice and …, 2017 - Wiley Online Library
Processor register file (RF) is an important microarchitectural component used for storing
operands and results of instructions. The design and operation of RF have crucial impact on …
operands and results of instructions. The design and operation of RF have crucial impact on …
An energy efficient wireless Network-on-Chip using power-gated transceivers
Networks-on-Chip (NoCs) have been accepted as scalable and efficient communication
backbone for many-core Systems-on-Chip (SoCs) by both the academia and the industry …
backbone for many-core Systems-on-Chip (SoCs) by both the academia and the industry …
DESCNet: Developing efficient scratchpad memories for capsule network hardware
Deep neural networks (DNNs) have been established as the state-of-the-art method for
advanced machine learning applications. Recently proposed by the Google Brain's team …
advanced machine learning applications. Recently proposed by the Google Brain's team …
Power optimization using clock gating and power gating: A review
The scaling of CMOS technology has continued due to ever increasing demand of greater
performance with low power consumption. This demand has grown further by the portable …
performance with low power consumption. This demand has grown further by the portable …
Application-guided power gating reducing register file static power
H Tabkhi, G Schirner - IEEE Transactions on Very Large Scale …, 2014 - ieeexplore.ieee.org
Power and energy efficiency are on the top priority list in embedded computing. Embedded
processors taped out in deep submicron technology have a high contribution of static power …
processors taped out in deep submicron technology have a high contribution of static power …
Agilewatts: An energy-efficient cpu core idle-state architecture for latency-sensitive server applications
User-facing applications running in modern datacenters exhibit irregular request patterns
and are implemented using a multitude of services with tight latency requirements (30–250 μ …
and are implemented using a multitude of services with tight latency requirements (30–250 μ …
Active mode subclock power gating
This paper presents a technique, called subclock power gating, for reducing leakage power
during the active mode in low performance, energy-constrained applications. The proposed …
during the active mode in low performance, energy-constrained applications. The proposed …
Adaptive power management of on-chip video memory for multiview video coding
An adaptive power management of on-chip video memory for Multiview Video Coding is
presented. It leverages texture, motion and disparity properties of objects and their …
presented. It leverages texture, motion and disparity properties of objects and their …
A low-power memory architecture with application-aware power management for motion & disparity estimation in multiview video coding
A low-power architecture for an on-chip multi-banked video memory for motion and disparity
estimation in Multiview Video Coding is proposed. The memory organization (size, banks …
estimation in Multiview Video Coding is proposed. The memory organization (size, banks …
Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI
Scaling down of CMOS Technology reduces supply voltage which helps evade device botch
caused by high electric fields in the conducting channel under the gate and gate oxide …
caused by high electric fields in the conducting channel under the gate and gate oxide …