A 16-bit 16-MS/s SAR ADC with on-chip calibration in 55-nm CMOS

J Shen, A Shikata, LD Fernando… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper presents a successive approximation register (SAR) analog-to-digital converter
(ADC) that is much smaller and faster than other recently reported precision (16-bit and …

A mismatch calibration technique for SAR ADCs based on deterministic self-calibration and stochastic quantization

M Bagheri, F Schembari… - … on Circuits and …, 2020 - ieeexplore.ieee.org
A capacitive DAC is an important building block of a charge-redistribution SAR ADC, for its
size has a significant impact on performance. For medium-to high-resolution applications …

A short review of some analog-to-digital converters resolution enhancement methods

Y Zheng, Y Zhao, N Zhou, H Wang, D Jiang - Measurement, 2021 - Elsevier
The resolution of the analog-to-digital converter (ADC), ie the minimum voltage that ADC
can recognize, is an important indicator of ADC performance. In order to improve the …

A digital-domain calibration of split-capacitor DAC for a differential SAR ADC without additional analog circuits

JY Um, YJ Kim, EW Song, JY Sim… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
A digital-domain calibration method is proposed for a split-capacitor DAC (split-CDAC) used
in a differential-type 11-bit SAR ADC. It calibrates the nonlinearities of SAR ADC due to the …

LAYGO: A template-and-grid-based layout generation engine for advanced CMOS technologies

J Han, W Bae, E Chang, Z Wang… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for
enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is …

A 5-GS/s 10-b 76-mW time-interleaved SAR ADC in 28 nm CMOS

J Fang, S Thirunakkarasu, X Yu… - … on Circuits and …, 2017 - ieeexplore.ieee.org
This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation
register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along …

A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC with opamp-less time-domain integrator

SE Hsieh, CC Hsieh - IEEE Journal of Solid-State Circuits, 2019 - ieeexplore.ieee.org
This paper presents a 13-bit high-resolution two-step analog-to-digital converter (ADC).
Successive approximation register (SAR)-ADCs and an incremental sigma-delta modulator …

A signal-independent background-calibrating 20b 1MS/S SAR ADC with 0.3 ppm INL

H Li, M Maddox, MCW Coin, W Buckley… - … Solid-State Circuits …, 2018 - ieeexplore.ieee.org
The SAR ADC is the architecture of choice for high-precision Nyquist ADCs (> 16b) with
MS/s speed. To achieve the required linearity performance, precision SAR ADCs require …

A high area-efficiency 14-bit SAR ADC with hybrid capacitor DAC for array sensors

Q Zhang, N Ning, J Li, Q Yu, Z Zhang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
This paper proposes a high area-efficiency 14-bit column-parallel successive approximation
register (SAR) analog-to-digital converter (ADC) for array sensors. A novel hybrid capacitor …

A 10-b ternary SAR ADC with quantization time information utilization

J Guerber, H Venkatram, M Gande… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
The design of a ternary successive approximation (TSAR) analog-to-digital converter (ADC)
with quantization time information utilization is proposed. The TSAR examines the transient …