The performance of high-speed wireline data links depend crucially on the quality and
precision of their clocking infrastructure. For future applications, such as microprocessor …

Clock and data recovery (CDR) architectures used in high-speed wire-linked communication
receivers are often shown as PLL or DLL based topologies. However, there are many other …

The distribution and alignment of high-frequency clocks across a wide bus of links is a
significant challenge in modern computing systems. A low power clock source is …

A general model for injection-locked LC oscillators (LC-ILOs) is presented that is valid for
any tank quality factor and injection strength. Important properties of an ILO such as lock …

In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across
40''of FR4 copper backplane traces and two connectors is described. The transmitter …

A low phase noise, delay-locked loop-based programmable frequency multiplier, with the
multiplication ratio from 13 to 20 and output frequency range from 900 MHz to 2.9 GHz, is …

The paper presents an analysis of the injection locking phenomenon in CMOS ring
oscillators. Adler's equation in injection locking is proved for a three-stage ring oscillator and …

A high-frequency jitter tolerant receiver in 65 nm CMOS is presented. Jitter tolerance is
improved by tracking correlated jitter using a pulsed clock forwarded from the transmitter …

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter
suppression and phase interpolation in high-bandwidth system-on-chip solutions is …

This paper presents a distributed differential oscillator global clock network where the clock
capacitance is rendered resonant with a set of on-chip spiral inductors. The clock amplitude …