[57] ABSTRACT An array (10) of multi-level? oating gate memory cells includes wordlines
(18) connected to memory cells along a row in the array, and bit lines (12) connected to …

This application is a divisional of US application Ser. No. 09/641,693, filed Aug. 18, 2000
now US Pat. No. 6,601,191 which is a continuation of US patent application Ser. No …

Lione (57) ABSTRACT A method of erasing a memory cell that has a first region and a
Second region with a channel therebetween and a gate above the channel, and a charge …

US6278632B1 - Method and circuitry for performing analog over-program and under-program
detection for a multistate memory cell - Google Patents US6278632B1 - Method and circuitry …

A method for detecting an under-programming or over-programming condition in a multistate
memory cell. The method uses three sense amplifiers, each with an associated reference …

Rosati 57 ABSTRACT A page mode flash memory or floating gate memory device, includes
a page buffer based on low current bit latches. The low current bit latches enable efficient …

5,283,758 2/1994 Nakayama et al.... 365/185 coupled to a set of floating gate memory cells
in the memory, 5,294,819 3/1994 Simko.................. 257/314 a method of writing to a Selected …

Flash EEPROM cell and array designs, and methods for programming the same result in
efficient and accurate pro gramming of a flash EEPROM chip. The flash EEPROM chip …

BACKGROUND Electrically erasable and programmable memory devices having arrays of
what are known as multi-bit or multi-State flash cells are found in a wide variety of electrical …

In conventional Single-bit per cell memory devices, the memory cell assumes one of two
information Storage States, either an “on” state or an “off” state. The binary condition of “on” …