Silicon photonic transceivers for application in data centers

H Wang, H Chai, Z Lv, Z Zhang, L Meng… - Journal of …, 2020 - iopscience.iop.org
Global data traffic is growing rapidly, and the demand for optoelectronic transceivers applied
in data centers (DCs) is also increasing correspondingly. In this review, we first briefly …

A 243-mW 1.25–56-Gb/s continuous range PAM-4 42.5-dB IL ADC/DAC-based transceiver in 7-nm FinFET

M Pisati, F De Bernardinis, P Pascale… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
This article presents a compact analog-to-digital converter (ADC)/digital-to-analog converter
(DAC) digital signal processing (DSP)-based long reach (LR) transceiver in 7-nm FinFET …

Silicon-interconnect fabric for fine-pitch (≤ 10 μm) heterogeneous integration

SC Jangam, SS Iyer - IEEE Transactions on Components …, 2021 - ieeexplore.ieee.org
The apparent saturation of aggressive Moore's law scaling of semiconductor technologies is
pushing the boundaries of traditional packaging and integration schemes to accommodate …

A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS

A Atharav, B Razavi - IEEE Journal of Solid-State Circuits, 2021 - ieeexplore.ieee.org
A wireline receiver consisting of a linear equalizer, a decision-feedback equalizer (DFE), a
clock and data recovery (CDR) circuit, and a demultiplexer (DMUX) employs new circuit and …

Design techniques for 48-Gb/s 2.4-pJ/b PAM-4 baud-rate CDR with stochastic phase detector

H Ju, K Lee, K Park, W Jung… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This article presents design techniques for a PAM-4 baud-rate digital clock and data
recovery (CDR) circuit utilizing a stochastic phase detector (SPD). The proposed baud-rate …

A 50–112-Gb/s PAM-4 transmitter with a fractional-spaced FFE in 65-nm CMOS

X Zheng, H Ding, F Zhao, D Wu, L Zhou… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
This article presents a 50–112-Gb/s current-mode four-level pulse amplitude modulation
(PAM-4) transmitter with a two-tap fractional-spaced feed-forward equalizer (FFE). The …

A wide tuning range dual-core quad-mode orthogonal-coupled VCO with concurrently dual-output using parallel 8-shaped resonator

S Sun, W Deng, H Jia, R Wu, C Li… - IEEE Transactions …, 2022 - ieeexplore.ieee.org
This article presents a dual-core quad-mode orthogonal-coupled wide frequency tuning
range voltage-controlled oscillator (VCO) using mode control switches to realize the …

A 56-Gb/s PAM-4 transmitter/receiver chipset with nonlinear FFE for VCSEL-based optical links in 40-nm CMOS

PJ Peng, PL Lee, HE Huang, WJ Huang… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
This article presents a 56-Gb/s four-level pulse amplitude modulation (PAM-4)
transmitter/receiver (TX/RX) chipset for optical link. The optical transmitter (TX) adopts a …

A 112-Gb/s PAM-4 voltage-mode transmitter with four-tap two-step FFE and automatic phase alignment techniques in 40-nm CMOS

PJ Peng, YT Chen, ST Lai… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) voltage-
mode transmitter (TX) with a four-tap feed-forward equalizer (FFE). A two-step coarse-/fine …

A 32-Gb/s 0.46-pJ/bit PAM4 CDR using a quarter-rate linear phase detector and a self-biased PLL-based multiphase clock generator

Z Zhang, G Zhu, C Wang, L Wang… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
This article presents a four-level pulse-amplitude modulation (PAM4) quarter-rate clock and
data recovery circuit (CDR). A quarter-rate linear phase detector (QLPD) is proposed to …