Heterogeneous FPGA+ GPU embedded systems: Challenges and opportunities
M Hosseinabady, MAB Zainol… - arXiv preprint arXiv …, 2019 - arxiv.org
The edge computing paradigm has emerged to handle cloud computing issues such as
scalability, security and low response time among others. This new computing trend heavily …
scalability, security and low response time among others. This new computing trend heavily …
Design and evaluation of floating point matrix operations for FPGA based system design
S Chetan, KS Sourabh, V Lekshmi, S Sudhakar… - Procedia Computer …, 2020 - Elsevier
Matrices are considered as the heart of different applications in several scientific fields such
as solving electrical circuits, image processing, optimization, control systems, quantum …
as solving electrical circuits, image processing, optimization, control systems, quantum …
Design and FPGA Implementation of Matrix Multiplier Using DEMUX-RCA-Based Vedic Multiplier
Matrix multiplication is a common technique for increasing the computational speed of
scientific and engineering tasks. The matrix multiplier is designed in this paper utilizing an …
scientific and engineering tasks. The matrix multiplier is designed in this paper utilizing an …
Digital Architecture for the n-mode Tensor-Matrix Multiplication Based on Pipelined Computing Units
Compact digital circuitry supporting data processing is a key requirement of modern
engineering. This pa-per addresses the design of digital architectures for a crucial operation …
engineering. This pa-per addresses the design of digital architectures for a crucial operation …
Performance evaluation and tuning of an opencl based matrix multiplier
Matrix multiplication is one of the fundamental building blocks of numerical linear algebra. It
requires computer systems have huge computing capability and consumes much more …
requires computer systems have huge computing capability and consumes much more …
Design of an FPGA-based matrix multiplier with task parallelism
Matrix multiplication requires computer systems have huge computing capability and data
throughputs as problem size is increased. In this research, an OpenCL-based matrix …
throughputs as problem size is increased. In this research, an OpenCL-based matrix …
A Pipelined Implementation of the -mode Tensor-Matrix Multiplication
This paper tackles the design of a pipelined digital architecture supporting the n-mode
tensor-matrix product in the fixed-point representation. The solution balances throughput …
tensor-matrix product in the fixed-point representation. The solution balances throughput …
Design and FPGA Implementation of Matrix Multiplier Using DEMUX-RCA-Based Vedic Multiplier
BMYKA Mohammed, S Kumar… - Proceedings of the …, 2022 - books.google.com
Matrix multiplication is a common technique for increasing the computational speed of
scientific and engineering tasks. The matrix multiplier is designed in this paper utilizing an …
scientific and engineering tasks. The matrix multiplier is designed in this paper utilizing an …
Efficient digital implementation of n-mode tensor-matrix multiplication
With the growth of pervasive electronics, the availability of compact digital circuitry for the
support of data processing is becoming a key requirement. This paper tackles the design of …
support of data processing is becoming a key requirement. This paper tackles the design of …
Implementation of 3-D multiple linear regression in hardware using the xilinx spartan-3AN FPGA
I Grout, WAP Ferreira… - 2019 16th International …, 2019 - ieeexplore.ieee.org
In this paper, a linear regression algorithm implementation in hardware using the Field
Programmable Gate Array (FPGA) is presented. A two-dimensional (2-D) simple linear …
Programmable Gate Array (FPGA) is presented. A two-dimensional (2-D) simple linear …