In this paper, a novel framework is introduced to estimate the max-delay variability in logic
paths due to variations in a back-of-the-envelope fashion, thus allowing quick evaluation of …

Despite the fast advances in high-sigma yield analysis with the help of machine learning
techniques in the past decade, one of the main challenges, the curse of" dimensionality" …

There is a consistent dependence between integrated circuits (ICs) performance parameters
and manufacturing process variations and capturing it at an early development phase …

Statistical model checking (SMC) is a simulation-based approach for verifying the statistical
properties of large, complex systems. If a large number of low-probability events (rare …

In advanced CMOS technology, process, voltage, and temperature (PVT) variations increase
the paths' latency in digital circuits, especially when operating at a low supply voltage. The …

Considerable effort has been expended in the EDA community during the past decade in
trying to cope with the so-called statistical timing problem. In this paper, we not only present …

This paper presents a novel methodology for generating machine learning models used by
an adaptive Monte Carlo analysis. The advantages of this methodology are that model …

As the semiconductor technology scales down to 45nm and below, process variations have
a profound effect on SRAM cells and an urgent need is to develop fast statistical tools which …

Yield estimation has been and will continue to be the integral part in design flow, particularly
under large process variability in advanced technology nodes. This paper proposes an …

Monte Carlo (MC) analysis is often considered a golden reference for yield analysis
because of its high accuracy. However, repeating the simulation hundreds of times is often …