System, method, and computer program product for improving memory systems
MS Smith - US Patent 9,432,298, 2016 - Google Patents
H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid
state devices; Multistep manufacturing processes thereof the devices being of types …
state devices; Multistep manufacturing processes thereof the devices being of types …
Electrical Modeling and Design for 3D System Integration: 3D Integrated Circuits and Packaging, Signal Integrity, Power Integrity and EMC
EP Li - 2012 - books.google.com
New advanced modeling methods for simulating the electromagnetic properties of complex
three-dimensional electronic systems Based on the author's extensive research, this book …
three-dimensional electronic systems Based on the author's extensive research, this book …
Can we go towards true 3-D architectures?
PE Gaillardon, H Ben-Jamaa, PH Morel… - Proceedings of the 48th …, 2011 - dl.acm.org
Thanks to recent technology advances, the exploration of the vertical dimension has been
shown to be more than a dream for designers. Among those technologies, the vertical …
shown to be more than a dream for designers. Among those technologies, the vertical …
3D-MAPS: 3D massively parallel processor with stacked memory
SK Lim, SK Lim - Design for High Performance, Low Power, and …, 2013 - Springer
This chapter describes the architecture, design, analysis, and simulation and measurement
results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built …
results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built …
[图书][B] Through silicon vias: materials, models, design, and performance
Recent advances in semiconductor technology offer vertical interconnect access (via) that
extend through silicon, popularly known as through silicon via (TSV). This book provides a …
extend through silicon, popularly known as through silicon via (TSV). This book provides a …
High-frequency modeling of TSVs for 3-D chip integration and silicon interposers considering skin-effect, dielectric quasi-TEM and slow-wave modes
I Ndip, B Curran, K Lobbicke… - IEEE transactions on …, 2011 - ieeexplore.ieee.org
Through-silicon vias (TSVs) in low, medium and high resistivity silicon for 3-D chip
integration and interposers are modeled and thoroughly characterized from 100 MHz to 130 …
integration and interposers are modeled and thoroughly characterized from 100 MHz to 130 …
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to
offer new levels of efficiency, power, performance, and form-factor advantages over the …
offer new levels of efficiency, power, performance, and form-factor advantages over the …
PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and chip-PDN models
The impedance of a power-distribution network (PDN) in three-dimensionally stacked chips
with multiple through-silicon-via (TSV) connections (a 3D TSV IC) was modeled and …
with multiple through-silicon-via (TSV) connections (a 3D TSV IC) was modeled and …
A design tradeoff study with monolithic 3D integration
C Liu, SK Lim - Thirteenth International Symposium on Quality …, 2012 - ieeexplore.ieee.org
This paper studies various design tradeoffs existing in the monolithic 3D integration
technology. Different design styles in monolithic 3D ICs are studied, including transistor …
technology. Different design styles in monolithic 3D ICs are studied, including transistor …
Challenges and emerging solutions in testing TSV-based 2 1 over 2D-and 3D-stacked ICs
EJ Marinissen - 2012 Design, Automation & Test in Europe …, 2012 - ieeexplore.ieee.org
Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical
interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5 …
interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5 …