A novel test pattern generation method for multiple dc and ac faults is presented. The fault
models considered include line stuck-at, bridging, transition, and transistor stuck-open faults …

This paper presents an in-depth analysis of resistive open and resistive bridge defects
behavior under process, voltage and temperature (PVT) variation using delay test. Using …

The increasing complexity of manufacturing processes makes today's integrated circuits
more prone to defects such as resistive shorts and opens and also exacerbates the problem …

A dynamic bridging fault (DBF) induces a transition delay on a circuit node and hence has
fault effects similar to a transition delay fault (TDF). However the causes of these two types of …

SPICE offers an accurate method of simulating defect behavior. However, as demonstrated
by recent research, it requires long computation time to simulate defect behavior, when …

A novel test pattern generation flow for both DC and AC faults is presented. All faults to be
processed are transformed into stuck-at faults with some constraints in a proposed two …

Bridge defects are an important manufacturing defect that may escape test causing reliability
issues. It has been shown that in nanometer regime, process variations pose important …

The transition delay faults (TDF) model has been widely used in industry to model time-
related defects. A dynamic bridging fault (DBF) also has similar delay effect. However, the …

As silicon manufacturing process scales to and beyond the 65-nm node, process variation
can no longer be ignored. The impact of process variation on integrated circuit performance …

The paper develops an efficient mechanism with a view to healing bridging faults in
synchronous sequential circuits. The scheme inserts faults randomly into the system at the …