Low-power and area-efficient carry select adder

B Ramkumar, HM Kittur - IEEE transactions on very large scale …, 2011 - ieeexplore.ieee.org
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing
processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that …

Area–delay–power efficient carry-select adder

BK Mohanty, SK Patel - … transactions on circuits and systems II …, 2014 - ieeexplore.ieee.org
In this brief, the logic operations involved in conventional carry select adder (CSLA) and
binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence …

An area efficient 64-bit square root carry-select adder for low power applications

Y He, CH Chang, J Gu - 2005 IEEE International Symposium …, 2005 - ieeexplore.ieee.org
The carry-select method has deemed to be a good compromise between cost and
performance in carry propagation adder design. However, the conventional carry-select …

An efficient SQRT architecture of carry select adder design by common Boolean logic

S Manju, V Sornagopal - 2013 International Conference on …, 2013 - ieeexplore.ieee.org
Carry Select adder (CSLA) is known to be the fastest adder among the Conventional adder
structures. This work uses an efficient Carry select adder by sharing the Common Boolean …

Design of high speed hybrid carry select adder

S Parmar, KP Singh - 2013 3rd IEEE International Advance …, 2013 - ieeexplore.ieee.org
The paper describes the power and area efficient carry select adder (CSA). Firstly, CSA is
one of the fastest adders used in many data-processing systems to perform fast arithmetic …

A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two's complement converter

Y He, CH Chang - IEEE Transactions on Circuits and Systems I …, 2008 - ieeexplore.ieee.org
This paper presents an efficient reverse converter for transforming the redundant binary (RB)
representation into two's complement form. The hierarchical expansion of the carry equation …

Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications

P Patali, ST Kassim - Microelectronics Journal, 2020 - Elsevier
Adders and multipliers are the fundamental elements of a signal processing architecture.
Improve the speed of addition and multiplication operations while minimizing power …

High throughput FIR filter architectures using retiming and modified CSLA based adders

P Patali… - IET Circuits, Devices & …, 2019 - Wiley Online Library
A methodology to improve the throughput of FIR filters through the effective use of retiming
and efficient add–multiply operation is presented in this study. Delay, energy and area …

Delay and energy efficient modular hybrid adder for signal processor architectures

P Pramod, TK Shahana - IETE Journal of Research, 2022 - Taylor & Francis
In this modern era, high-performance energy efficient devices/systems are the basic
requirement for most of the real-time applications. Multiply-accumulate (MAC) units are the …

An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit

GA Ruiz, M Granda - Microelectronics journal, 2004 - Elsevier
This paper presents a highly area-efficient CMOS carry-select adder (CSA) with a regular
and iterative-shared transistor structure very suitable for implementation in VLSI. This adder …