Advancing placement

AB Kahng - Proceedings of the 2021 International Symposium on …, 2021 - dl.acm.org
Placement is central to IC physical design: it determines spatial embedding, and hence
parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized …

Logic synthesis for low power

L Benini, G De Micheli - Logic Synthesis and Verification, 2002 - Springer
Energy-efficient design of integrated circuits requires specialized tools and technologies.
This chapter surveys some of the most important contributions in logic synthesis for …

Assembly-aware design of printable electromechanical devices

R Desai, J McCann, S Coros - Proceedings of the 31st Annual ACM …, 2018 - dl.acm.org
From smart toys and household appliances to personal robots, electromechanical devices
play an increasingly important role in our daily lives. Rather than relying on gadgets that are …

Incremental trace-buffer insertion for FPGA debug

E Hung, SJE Wilton - IEEE Transactions on Very Large Scale …, 2013 - ieeexplore.ieee.org
As integrated circuits encapsulate more functionality and complexity, verifying that these
devices operate correctly under all scenarios is an increasingly difficult task. Rather than …

Optimizing integrated circuit design through use of sequential timing information

C Albrecht, P Chong, A Kuehlmann… - US Patent …, 2010 - Google Patents
(57) ABSTRACT A method is provided that includes: determining a minimum clock cycle that
can be used to propagate a signal about the critical cycle in a circuit design; wherein the …

Data path and placement optimization in an integrated circuit through use of sequential timing information

C Albrecht, P Chong, A Kuehlmann… - US Patent …, 2009 - Google Patents
A method is provided that includes: determining a minimum clock cycle that can be used to
propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a …

Optimizing integrated circuit design through balanced combinational slack plus sequential slack

C Albrecht - US Patent 7,739,642, 2010 - Google Patents
A method is provided that includes: determining a minimum clock cycle that can be used to
propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a …

TILA-S: Timing-driven incremental layer assignment avoiding slew violations

D Liu, B Yu, S Chowdhury… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
As very large scale integration technology scales to deep submicrometer and beyond,
interconnect delay greatly limits the circuit performance. The traditional 2-D global routing …

TAPHS: Thermal-aware unified physical-level and high-level synthesis

Z Gu, Y Yang, J Wang, RP Dick, L Shang - … of the 2006 Asia and South …, 2006 - dl.acm.org
Thermal effects are becoming increasingly important during integrated circuit design.
Thermal characteristics influence reliability, power consumption, cooling costs, and …

A statistical gate sizing method for timing yield and lifetime reliability optimization of integrated circuits

SM Ebrahimipour, B Ghavami… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
As CMOS devices become smaller, process and aging variations become a major issue for
circuit reliability and yield. In this paper, we propose a new two-phase gate sizing approach …