In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal
processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer …

US PATENT DOCUMENTS 7,193,433 B1* 3/2007 Young......................... 326/38 7,194,598
B2 3/2007 Jacob 5,572.207 A 1 1/1996 Harding et al. 7,197.686 B2 3/2007 Box et al …

US7301541B2 - Programmable processor and method with wide operations - Google Patents
US7301541B2 - Programmable processor and method with wide operations - Google Patents …

Described are mathematical circuits that perform flexible rounding schemes. The circuits
require few additional resources and can be adjusted dynamically to change the number of …

(57) ABSTRACT A method for detecting a pattern from an arithmetic logic unit (ALU) in an
integrated circuit. The method includes the steps of generating an output from an ALU …

An integrated circuit for pattern detection including: an arith metic logic unit coupled to a
comparison circuit, where the arithmetic logic unit is programmed by an opcode; a selected …

First worldwide family litigation filed litigation https://patents. darts-ip. com/? family=
29273786&utm_source= google_patent&utm_medium= platform_link&utm_campaign …

The present invention provides a System and method for improving the performance of
general purpose processors by expanding at least one Source operand to a width greater …

Int. Cl. G06F 7/48(2006.01) Described are arithmetic circuits divided logically into a (52) US
Cl........................................ 708/523: 708/501 product generator and an adder. Multiplexing …

A programmable processor that comprises a general purpose processor architecture,
capable of operation independent of another host processor, having a virtual memory …