10-bit 30-MS/s SAR ADC using a switchback switching method
This brief presents a 10-bit 30-MS/s successive-approximation-register analog-to-digital
converter (ADC) that uses a power efficient switchback switching method. With respect to the …
converter (ADC) that uses a power efficient switchback switching method. With respect to the …
A 9-bit 150-MS/s subrange ADC based on SAR architecture in 90-nm CMOS
This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-
bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a …
bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a …
Split-SAR ADCs: Improved linearity with power and speed optimization
This paper presents the linearity analysis of a successive approximation registers (SAR)
analog-to-digital converters (ADC) with split DAC structure based on two switching methods …
analog-to-digital converters (ADC) with split DAC structure based on two switching methods …
A 6-bit 50-MS/s threshold configuring SAR ADC in 90-nm digital CMOS
P Nuzzo, C Nani, C Armiento… - … on Circuits and …, 2011 - ieeexplore.ieee.org
A successive approximation analog-to-digital converter (ADC) architecture is presented that
programs its comparator threshold at runtime to approximate the input signal via binary …
programs its comparator threshold at runtime to approximate the input signal via binary …
An Ultra Low-Power Programmable Voltage Reference for Power-Constrained Electronic Systems
M Caselli, E Tiurin, S Stanzione… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This paper proposes a novel architecture for the generation of a programmable voltage
reference: the background-calibrated (BC)-PVR. Our mixed-signal architecture periodically …
reference: the background-calibrated (BC)-PVR. Our mixed-signal architecture periodically …
A 70-MS/s Vcm-free 10-bit-resolution SAR ADC with a novel DAC structure to reduce area andparasitic capacitance effect
MVP Aghdami, M Mousazadeh, J Sobhi… - … -International Journal of …, 2022 - Elsevier
A 10-bit-resolution successive approximation ADC with 70-Ms/s conversion rate and with a
new configuration for capacitive DAC is represented in this paper. In the DAC structure …
new configuration for capacitive DAC is represented in this paper. In the DAC structure …
Determining the reliable minimum unit capacitance for the DAC capacitor array of SAR ADCs
X Yue - Microelectronics Journal, 2013 - Elsevier
The layout area of an SAR ADC is mainly occupied by its DAC capacitor array. Since there
are 2N matched unit capacitors employed for a binary-weighted N-bit DAC, selecting a small …
are 2N matched unit capacitors employed for a binary-weighted N-bit DAC, selecting a small …
Design of hybrid resistive-capacitive DAC for SAR A/D converters
B Sedighi, AT Huynh, E Skafidas… - 2012 19th IEEE …, 2012 - ieeexplore.ieee.org
While hybrid capacitive-resistive D/A Converter (DAC) has been known for many years, its
potential for energy-efficient operation is sometimes overlooked. This paper investigates the …
potential for energy-efficient operation is sometimes overlooked. This paper investigates the …
Segmented architecture for successive approximation analog-to-digital converters
In this paper, the structure of a binary-weighted capacitive digital-to-analog converter (DAC)
in a successive-approximation analog-to-digital converter (SA-ADC) is modified to a unary …
in a successive-approximation analog-to-digital converter (SA-ADC) is modified to a unary …
Introduction: The Oralization of Digital Written Communication
C Cutler, M Ahmar, S Bahri - Digital Orality: Vernacular Writing in Online …, 2022 - Springer
An increasing part of informal human communication is taking place through the modality of
digital writing. Much of this writing reflects a hybrid style combining both oral and written …
digital writing. Much of this writing reflects a hybrid style combining both oral and written …