SPTF: a scalable probabilistic tensor factorization model for semantic-aware behavior prediction

H Yin, H Chen, X Sun, H Wang, Y Wang… - … Conference on Data …, 2017 - ieeexplore.ieee.org
With the rapid rise of various e-commerce and social network platforms, users are
generating large amounts of heterogeneous behavior data, such as purchasehistory, adding …

Decimal multiplication via carry-save addition

MA Erle, MJ Schulte - Proceedings IEEE International …, 2003 - ieeexplore.ieee.org
Decimal multiplication is important in many commercial applications including financial
analysis, banking, tax calculation, currency conversion, insurance, and accounting. We …

Decimal multiplication with efficient partial product generation

MA Erle, EM Schwarz… - 17th IEEE Symposium on …, 2005 - ieeexplore.ieee.org
Decimal multiplication is important in many commercial applications including financial
analysis, banking, tax calculation, currency conversion, insurance, and accounting. This …

Improved design of high-performance parallel decimal multipliers

A Vazquez, E Antelo… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
The new generation of high-performance decimal floating-point units (DFUs) is demanding
efficient implementations of parallel decimal multipliers. In this paper, we describe the …

Design of high speed BCD adder using CMOS technology

A Al Share, FN Zghoul, O Al-Khaleel… - IEEE …, 2023 - ieeexplore.ieee.org
Decimal arithmetic gains its importance in different applications in the fields of finance and
scientific applications. The approach of running decimal arithmetic over binary hardware …

Decimal full adders specially designed for quantum-dot cellular automata

D Abedi, G Jaberipur - … Transactions on Circuits and Systems II …, 2017 - ieeexplore.ieee.org
New emerging technologies, with low area/power/latency properties, are gaining momentum
as replacements for CMOS. In particular, for quantum-dot cellular automata (QCA) …

Improving the speed of parallel decimal multiplication

G Jaberipur, A Kaivani - IEEE Transactions on Computers, 2009 - ieeexplore.ieee.org
Hardware support for decimal computer arithmetic is regaining popularity. One reason is the
recent growth of decimal computations in commercial, scientific, financial, and Internet …

Binary-coded decimal digit multipliers

G Jaberipur, A Kaivani - IET Computers & Digital Techniques, 2007 - IET
With the growing popularity of decimal computer arithmetic in scientific, commercial,
financial and Internet-based applications, hardware realisation of decimal arithmetic …

Decimal floating-point support on the IBM System z10 processor

EM Schwarz, JS Kapernick… - IBM Journal of Research …, 2009 - ieeexplore.ieee.org
The latest IBM zSeries® processor, the IBM System z10™ processor, provides hardware
support for the decimal floating-point (DFP) facility that was introduced on the IBM System …

A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format

M Cornea, J Harrison, C Anderson… - IEEE transactions on …, 2008 - ieeexplore.ieee.org
The IEEE Standard 754-1985 for binary floating-point arithmetic [19] was revised [20], and
an important addition is the definition of decimal floating-point arithmetic [8],[24]. This is …