Design space exploration of non-uniform cache access for soft-error vulnerability mitigation

M Maghsoudloo, HR Zarandi - Microelectronics Reliability, 2015 - Elsevier
In this paper, the design space exploration problem is concerned with finding the best
composition of different Non-Uniform Cache Access (NUCA) specifications in many-core …

Memory-aware design space exploration for reliability evaluation in computing systems

M Kooli, G Di Natale, A Bosio - Journal of Electronic Testing, 2019 - Springer
In this paper, we present an analytical methodology to measure the vulnerability of the
memory components of a microprocessor-based computing system. It is based on the data …

Stability investigation for 1R-2W and 2R-2W Register File SRAM bit cell using FinFET in subthreshold region

S Mohan, KS Pande, NS Murty - 2015 International Conference …, 2015 - ieeexplore.ieee.org
Register Files (RF) are multi-port static memories with dedicated READ and WRITE ports for
high bandwidth memory operations. The Register Files are important components in today's …

Register file criticality on embedded microprocessor reliability

FM Lins, L Tambara, FL Kastensmidt… - 2016 16th European …, 2016 - ieeexplore.ieee.org
Register file criticality on embedded microprocessor reliability Page 1 Register File Criticality
on Embedded Microprocessor Reliability Filipe M. Lins, Lucas Tambara, Fernanda L …

Synthesis of Register Files for Low-Power Heterogeneous Digital Systems Based on FPGA

DL Oliveira, FF Nascimento, MH Victor… - 2023 IEEE Seventh …, 2023 - ieeexplore.ieee.org
Field Programmable Gated Array (FPGAs) devices are widely used today. Due to their high
integration, FPGAs are used in complex, energy-efficient digital projects. An important …

Multi objective design space exploration of cache for embedded applications

M Alipour, H Taghdisi… - 2012 25th IEEE …, 2012 - ieeexplore.ieee.org
High contribution of cache access power in the total power consumption of embedded
processors has made it a major concern in embedded system designs. By technology …

A Fast-and-Effective Early-Stage Multi-level Cache Optimization Method Based on Reuse-Distance Analysis

CL Tsai, RS Tsay - arXiv preprint arXiv:2109.04614, 2021 - arxiv.org
In this paper, we propose a practical and effective approach allowing designers to optimize
multi-level cache size at the early system design phase. Our key contribution is to generalize …

Analysing and supporting the reliability decision-making process in computing systems with a reliability evaluation framework

M Kooli - 2016 - theses.hal.science
Reliability has become an important design aspect for computing systems due to the
aggressive technology miniaturization and the increase of the non interrupted performance …

Instruction cache design space exploration for embedded software applications

R Patel, A Rajawat - … Symposium on VLSI Design and Test, 2015 - ieeexplore.ieee.org
Embedded processors with cache memories are used to improve the overall performance of
the system. To maintain a trade-off between cache size costs vs. performance, it is required …

Effect of thread level parallelism on the performance of optimum architecture for embedded applications

M Alipour, H Taghdisi - arXiv preprint arXiv:1204.2772, 2012 - arxiv.org
According to the increasing complexity of network application and internet traffic, network
processor as a subset of embedded processors have to process more computation intensive …