A New Method for Defining Monotone Staircases in VLSI Floorplans
B Kar, S Sur-Kolay, C Mandal - 2015 IEEE Computer Society …, 2015 - ieeexplore.ieee.org
Physical design of a chip typically entails the global routing (GR) step after detailed
placement. In this step, the grid graph (GG) model is used widely for the one or two-bend …
placement. In this step, the grid graph (GG) model is used widely for the one or two-bend …
Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model
B Kar, S Sur-Kolay, C Mandal - arXiv preprint arXiv:1810.12789, 2018 - arxiv.org
Multiple design iterations are inevitable in nanometer Integrated Circuit (IC) design flow until
desired printability and performance metrics are achieved. This starts with placement …
desired printability and performance metrics are achieved. This starts with placement …
STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction
B Kar, S Sur-Kolay, C Mandal - arXiv preprint arXiv:1810.10412, 2018 - arxiv.org
With aggressively shrinking process nodes, physical design methods face severe
challenges due to poor convergence and uncertainty in getting an optimal solution. An early …
challenges due to poor convergence and uncertainty in getting an optimal solution. An early …
An early global routing framework for uniform wire distribution in SoCs
B Kar, S Sur-Kolay, C Mandal - 2016 29th IEEE International …, 2016 - ieeexplore.ieee.org
System-on-Chips (SoC) are being used to realize multipurpose devices such as mobile
phones, consumer electronics which can connect over the internet. The design process …
phones, consumer electronics which can connect over the internet. The design process …