Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW
We compare SAT-checkers and decision diagrams on the evalua-tion of Boolean formulas
produced in the formal verification of both correct and buggy versions of superscalar and …
produced in the formal verification of both correct and buggy versions of superscalar and …
Defeating UCI: Building stealthy and malicious hardware
In previous work Hicks et al. proposed a method called Unused Circuit Identification (UCI)
for detecting malicious backdoors hidden in circuits at design time. The UCI algorithm …
for detecting malicious backdoors hidden in circuits at design time. The UCI algorithm …
Automatic test program generation: a case study
Design validation is a critical step in the development of present-day microprocessors, and
some authors suggest that up to 60% of the design cost is attributable to this activity. Of the …
some authors suggest that up to 60% of the design cost is attributable to this activity. Of the …
Microarchitecture verification by compositional model checking
R Jhala1, KL McMillan - … : 13th International Conference, CAV 2001 Paris …, 2001 - Springer
Compositional model checking is used to verify a processor microarchitecture containing
most of the features of a modern microprocessor, including branch prediction, speculative …
most of the features of a modern microprocessor, including branch prediction, speculative …
A symbolic approach to predicate abstraction
Predicate abstraction is a useful form of abstraction for the verification of transition systems
with large or infinite state spaces. One of the main bottlenecks of this approach is the …
with large or infinite state spaces. One of the main bottlenecks of this approach is the …
Systematic software-based self-test for pipelined processors
D Gizopoulos, M Psarakis, M Hatzimihail… - … Transactions on Very …, 2008 - ieeexplore.ieee.org
Software-based self-test (SBST) has recently emerged as an effective methodology for the
manufacturing test of processors and other components in systems-on-chip (SoCs). By …
manufacturing test of processors and other components in systems-on-chip (SoCs). By …
Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic
The logic of Equality with Uninterpreted Functions (EUF) provides a means of abstracting the
manipulation of data by a processor when verifying the correctness of its control logic. By …
manipulation of data by a processor when verifying the correctness of its control logic. By …
Putting it all together–Formal verification of the VAMP
S Beyer, C Jacobi, D Kröning, D Leinenbach… - International Journal on …, 2006 - Springer
In the verified architecture microprocessor (VAMP) project we have designed, functionally
verified, and synthesized a processor with full DLX instruction set, delayed branch …
verified, and synthesized a processor with full DLX instruction set, delayed branch …
Efficient translation of Boolean formulas to CNF in formal verification of microprocessors
MN Velev - ASP-DAC 2004: Asia and South Pacific Design …, 2004 - ieeexplore.ieee.org
We present a method for translating Boolean formulas to CNF by identifying gates with
fanout count of 1, and merging them with their fanout gate to generate a single set of …
fanout count of 1, and merging them with their fanout gate to generate a single set of …
Modeling and verification of out-of-order microprocessors in UCLID
In this paper, we describe the modeling and verification of out-of-order microprocessors with
unbounded resources using an expressive, yet efficiently decidable, quantifier-free fragment …
unbounded resources using an expressive, yet efficiently decidable, quantifier-free fragment …