A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate
The impact of alpha particle and exposure to cosmic radiation has multifold the existing
stability issue associated with modern sub-100 nm SRAM cell design. Noise insertion in the …
stability issue associated with modern sub-100 nm SRAM cell design. Noise insertion in the …
Design optimization of the complementary voltage controlled oscillator using a multi-objective gravitational search algorithm
SM Ebrahimi, MJ Hemmati - Evolving Systems, 2023 - Springer
Past decade has witnessed the progress of cross-coupled LC voltage controlled oscillator
(VCO) in both academic and industrial communities. In this work, a new multi-objective …
(VCO) in both academic and industrial communities. In this work, a new multi-objective …
Process variation tolerant wide-band fast PLL with reduced phase noise using adaptive duty cycle control strategy
This paper presents the effects of manufacturing process variations on the phase-locked
loop (PLL) performances like lock time, lock range and phase noise. At higher operating …
loop (PLL) performances like lock time, lock range and phase noise. At higher operating …
Design and performance analysis of current starved voltage controlled oscillator
In this paper, current starved voltage controlled oscillators (CSVCO) using CMOS 180 nm
technology are designed and their performances are evaluated. Then, a comparative study …
technology are designed and their performances are evaluated. Then, a comparative study …
Modelling and Optimization of Phase Locked Loop under Constrained Channel Length and Width of MOSFETs
CMOS integrated circuits consisting of MOSFETs have tradeoffs among their performance
parameters. Hence they need minimization in those tradeoffs calling for multi objective …
parameters. Hence they need minimization in those tradeoffs calling for multi objective …
High performance PLL for multiband GSM applications
Dead zone very often poses to be a limitation in the high performance phase locked loops
(PLLs). The design of a dead zone free PLL with fast locking and low phase noise capability …
(PLLs). The design of a dead zone free PLL with fast locking and low phase noise capability …
Performance-linked phase-locked loop architectures: recent developments
Performance of the phase-locked loop (PLL) dictates the quality of the communication
systems where it is used. It is desirable for the PLL to have fast locking, low noise, wide lock …
systems where it is used. It is desirable for the PLL to have fast locking, low noise, wide lock …