Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive
performance improvements over the past 10 years by incorporating strained silicon (Si) …

The adoption of Silicon-on-Insulator (SOI) substrates for the manufacturing of mainstream
semiconductor products such as microprocessors has given SOI research an …

Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS
leakage (ie, off-state) current. Threshold voltages of transistors have scaled to maintain …

In this study, an analytical model for surface potential and threshold voltage for undoped (or
lightly) doped tri-gate Fin Field Effect Transistor (TG-FinFET) is proposed and validated …

Hole transport in the p-type metal-oxide-semiconductor field-effect-transistor (⁠ p-MOSFET)
inversion layer under arbitrary stress, surface, and channel orientation is investigated by …

Due to the limited control of the short channel effects, the high junction leakage caused by
band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling …

In reactive-ion etching (RIE) of silicon oxide (SiO 2) or silicon nitride (SiN) by fluorocarbon
(FC) or hydrofluorocarbon (HFC) plasmas, fluorinated carbon layers may be formed on the …

The performance of next-generation, nanoelectronic devices relies on a precise
understanding of strain within the constituent materials. However, the increased flexibility …

This paper describes the performance of nMOS and pMOS tall triple gate (MUGFET) devices
with fin widths down to 20 nm fabricated for the first time on super critical strained Si on …

This paper presents both analytical models and Monte Carlo simulations concerning strain
engineering in n-type silicon FinFETs. Our analysis identifies the stress configurations and …