Thermal warpage analysis of PBGA mounted on PCB during reflow process by FEM and experimental measurement

W Xia, M Xiao, Y Chen, F Wu, Z Liu… - Soldering & Surface Mount …, 2014 - emerald.com
Purpose–The purpose of this paper is to study the thermal warpage of a plastic ball grid
array (PBGA) mounted on a printed circuit board (PCB) during the reflow process …

Effects of package warpage on head-in-pillow defect

Z Zhao, C Chen, CY Park, Y Wang, L Liu… - Materials …, 2015 - jstage.jst.go.jp
Down to the road of speed, complexity, and miniaturization, ball grid array (BGA) design has
been introduced into electronic industry due to its higher I/O density. However, the …

Effects of package design on top PoP package warpage

J Zhao, Y Luo, Z Huang, R Ma - 2008 58th Electronic …, 2008 - ieeexplore.ieee.org
In recent years, Package on Package (PoP), in which a top memory packaging system is
connected to a bottom logic package via solder joint, is a System-in-Package (SiP) solution …

Effects of material properties on PoP top package warpage behaviors

MJ Yim, R Strode, R Adimula… - 2010 Proceedings 60th …, 2010 - ieeexplore.ieee.org
Top package with stacked memory die connected to a bottom logic package via solder balls
is a representative PoP configuration. This POP configuration has become very popular in …

Overview of board-level solder joint reliability modeling for single die and stacked die CSPs

ZW Zhong, TY Tee - Proceedings of the IEEE, 2009 - ieeexplore.ieee.org
Modeling can efficiently investigate the reliability of new packages, saving time, manpower,
and cost for conducting actual tests; A good model is useful for short time-to-market. In this …

[PDF][PDF] 基于埋置式基板的3 犇 犕犆犕封装结构的研制

徐高卫, 吴燕红, 周健, 罗乐 - 半导体学报, 2008 - jos.ac.cn
研制一种用于无线传感网的多芯片组件(3 犇 犕犆犕). 采用层压, 开槽等工艺获得埋置式高密度
多层有机(犉犚 4) 基板, 通过板上芯片(犆犗犅), 板上倒装芯片(犉犆犗犅), 球栅阵列(犅犌犃) …

Impact of mold compound cure shrinkage on substrate block warpage simulation

M Lim, CL Yean, A Yeo, C Lee - 2006 Thirty-First IEEE/CPMT …, 2006 - ieeexplore.ieee.org
In this paper, four modeling approaches such as InsCTE, MeanCTE, EqvCTE and
CureCTE+ MeanCTE, were employed to predict the substrate warpage. Both laminate and …

Process-induced warpage and stress estimation of through glass via embedded interposer carrier with ring-type framework

PC Huang, YM Lin, HN Liu, CC Lee - Microelectronics Reliability, 2022 - Elsevier
The feasibility of embedded interposer carrier (EIC) has been proposed and developed to
improve the assembly process of three-dimensional (3D) integrated circuits (3D-ICs) …

Mechanically relevant chemical shrinkage of epoxy molding compounds

MF Sousa, O Hülck, T Braun, J Bauer… - … and Multi-Physics …, 2013 - ieeexplore.ieee.org
One of the most prominent failure modes in microelectronics devices is the delamination of
epoxy materials (adhesives, molding compounds). The thermal mismatch at the interface …

基于埋置式基板的三维多芯片组件的翘曲研究

徐高卫, 罗乐, 耿菲, 黄秋平, 周健 - 电子学报, 2009 - ejournal.org.cn
采用粘塑性有限元焊球模型以及大形变理论研究了三维多芯片组件(3D-MCM)
的翘曲形态特征及其成因, 结果表明基板腔室的存在使埋置式基板形成了双弓形翘曲形态 …