Single-electron transistor: review in perspective of theory, modelling, design and fabrication

R Patel, Y Agrawal, R Parekh - Microsystem Technologies, 2021 - Springer
Integrated circuit (IC) technology has grown tremendously over the last few decades. The
prime goal has been to achieve low-power and high-performance in logic and memory …

Technology and modeling of nonclassical transistor devices

GV Angelov, DN Nikolov… - Journal of Electrical and …, 2019 - Wiley Online Library
This paper presents a comprehensive outlook for the current technology status and the
prospective upcoming advancements. VLSI scaling trends and technology advancements in …

Design and simulation of hybrid CMOS–SET circuits

A Jana, NB Singh, JK Sing, SK Sarkar - Microelectronics Reliability, 2013 - Elsevier
Single electron devices have extremely poor driving capabilities so that direct application to
practical circuits is as yet almost impossible. A new methodology to overcome this problem …

Design and cryogenic operation of a hybrid quantum-CMOS circuit

P Clapera, S Ray, X Jehl, M Sanquer, A Valentian… - Physical Review …, 2015 - APS
Silicon-on-insulator nanowire transistors of very small dimensions exhibit electrostatic or
quantum effects like Coulomb blockade or single-dopant transport at low temperature. The …

SET logic driving capability and its enhancement in 3-D integrated SET–CMOS circuit

R Parekh, J Beauvais, D Drouin - Microelectronics Journal, 2014 - Elsevier
The driving capability of a single-electron transistor (SET) circuit is sensitive to the load and
interconnects. We discuss about improving the performance of a SET logic in hybrid SET …

A new SPICE macro model of single electron transistor for efficient simulation of single-electronics circuits

A Jain, A Ghosh, NB Singh, SK Sarkar - Analog Integrated Circuits and …, 2015 - Springer
To explore single-electron circuits for different applications, a proper simulation platform
where circuits consisting of single electron transistors and other devices can be simulated …

Design and implementation of SET-CMOS hybrid half subtractor

A Ghosh, A Jain, NB Singh… - 2014 Annual IEEE India …, 2014 - ieeexplore.ieee.org
A hybrid SET-CMOS based half subtractor is presented in this paper. Combination of CMOS
and SET technology facilitates new advantageous functionalities. The proposed hybrid SET …

Binary multiplication using hybrid MOS and multi-gate single-electron transistors

G Deng, C Chen - IEEE transactions on very large scale …, 2012 - ieeexplore.ieee.org
In this paper, we investigate the design of binary tree multipliers based on multi-input
counters using hybrid MOS and single-electron transistors (SETs). Our focus is on the …

Stability and reliability analysis of hybrid CMOS-SET circuits—a new approach

A Jain, A Ghosh, NB Singh… - Journal of Computational …, 2014 - ingentaconnect.com
A new approach for stability and reliability analysis of hybrid CMOS-SET circuits has been
proposed. Using this approach, the stability of hybrid SET-CMOS NAND and NOR gates has …

Supervised hidden Markov modeling for on-line handwriting recognition

JR Bellegarda, D Nahamoo, KS Nathan… - … of ICASSP'94. IEEE …, 1994 - ieeexplore.ieee.org
The performance of a large alphabet handwriting recognition system based on a
probabilistic framework is critically tied to the quality of the prototype distributions that are …