Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations

A Izraelevitz, J Koenig, P Li, R Lin… - 2017 IEEE/ACM …, 2017 - ieeexplore.ieee.org
Enabled by modern languages and retargetable compilers, software development is in a
virtual “Cambrian explosion” driven by a critical mass of powerfully parameterized libraries; …

DaDianNao: A neural network supercomputer

T Luo, S Liu, L Li, Y Wang, S Zhang… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
Many companies are deploying services largely based on machine-learning algorithms for
sophisticated processing of large amounts of data, either for consumers or industry. The …

Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse

MB Taylor - Proceedings of the 49th annual design automation …, 2012 - dl.acm.org
Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can
switch at full frequency is dropping exponentially with each process generation. This …

Toward dark silicon in servers

N Hardavellas, M Ferdman, B Falsafi, A Ailamaki - IEEE Micro, 2011 - ieeexplore.ieee.org
Server chips will not scale beyond a few tens to low hundreds of cores, and an increasing
fraction of the chip in future technologies will be dark silicon that we cannot afford to power …

A landscape of the new dark silicon design regime

MB Taylor - IEEE Micro, 2013 - ieeexplore.ieee.org
Because of the breakdown of Dennard scaling, the percentage of a silicon chip that can
switch at full frequency drops exponentially with each process generation. This utilization …

Computing in the dark silicon era: Current trends and research challenges

M Shafique, S Garg - IEEE Design & Test, 2016 - ieeexplore.ieee.org
Computing in the Dark Silicon Era: Current Trends and Research Challenges Page 1 2168-2356
(c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE …

The EDA challenges in the dark silicon era: Temperature, reliability, and variability perspectives

M Shafique, S Garg, J Henkel… - Proceedings of the 51st …, 2014 - dl.acm.org
Technology scaling has resulted in smaller and faster transistors in successive technology
generations. However, transistor power consumption no longer scales commensurately with …

Partitioning and offloading in smart mobile devices for mobile cloud computing: State of the art and future directions

F Gu, J Niu, Z Qi, M Atiquzzaman - Journal of Network and Computer …, 2018 - Elsevier
Mobile applications, such as augment reality, natural language processing, object
recognition and multimedia-based services, are becoming increasingly ubiquitous and can …

Cherry-picking: Exploiting process variations in dark-silicon homogeneous chip multi-processors

B Raghunathan, Y Turakhia, S Garg… - … Design, Automation & …, 2013 - ieeexplore.ieee.org
It is projected that increasing on-chip integration with technology scaling will lead to the so-
called dark silicon era in which more transistors are available on a chip than can be …

QsCores: Trading dark silicon for scalable energy efficiency with quasi-specific cores

G Venkatesh, J Sampson, N Goulding-Hotta… - Proceedings of the 44th …, 2011 - dl.acm.org
Transistor density continues to increase exponentially, but power dissipation per transistor is
improving only slightly with each generation of Moore's law. Given the constant chip-level …