Recently, there has been enormous attention given to the network on chip (NoC) because it
is scalable compared to the communication bus. Three dimensional (3D) NoC is getting …

TSV-to-TSV coupling is known to be a significant detriment to signal integrity in three-
dimensional (3D) IC architectures. Designing a reliable Through-Silicon Via is critical in …

An interesting style for SoC (Systems-on-Chip) circuit design is the GALS (Globally
Asynchronous, Locally Synchronous) paradigm, but its major drawback shows to be the …

Nowadays, digital circuits lead to low-power consumption, high performance, reuse, etc.
These circuits are typically synthesized in the synchronous paradigm, where the global clock …

The GALS (Globally Asynchronous, Locally Synchronous) style can be an interesting
alternative to complex digital systems that can be based on the “System-on-Chip-SoC” …

Many-core systems are of great importance for building the exascale computing machine
targeted for 2020. Last-Level Cache (LLC), as the largest on-chip shared memory in many …

Technology scaling and higher operational frequencies are no longer sustainable at the
same pace as before. The processor industry is rapidly moving from a single core with high …

Like every other major changes in computer architecture, exascale computing, targeted for
2020, requires dramatic and unanticipated shifts in different perspectives. The biggest …

Power has replaced performance as the primary constraint in modern digital circuits. The
advances in process technology have allowed billions of transistors to be put on a single …