Low latency reconfiguration mechanism for fine-grained processor internal functional units

RS Ferreira, J Nolte - 2019 IEEE Latin American Test …, 2019 - ieeexplore.ieee.org
The strive for performance, low power consumption, and less chip area have been
diminishing the reliability and the time to fault occurrences due to wear out of electronic …

Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation

JP Acle, R Cantoro, E Sánchez, MS Reorda… - Microprocessors and …, 2016 - Elsevier
The usage of electronic systems in safety-critical applications requires mechanisms for the
early detection of faults affecting the hardware while the system is in the field. When the …

Deterministic cache-based execution of on-line self-test routines in multi-core automotive system-on-chips

A Floridia, TM Carmona, D Piumatti… - … , Automation & Test …, 2020 - ieeexplore.ieee.org
Traditionally, the usage of caches and deterministic execution of on-line self-test procedures
have been considered two mutually exclusive concepts. At the same time, software executed …

In-field functional test programs development flow for embedded FPUs

R Cantoro, D Piumatti, P Bernardi… - … on Defect and Fault …, 2016 - ieeexplore.ieee.org
Software-Based Self-Test (SBST) is a recognized technique for in-field testing of
microcontrollers that are used in safety critical environments. In this paper, we describe …

On-chip dynamic resource management

A Miele, A Kanduri, K Moazzemi… - … and Trends® in …, 2019 - nowpublishers.com
The need for dynamic resource management has shadowed the exponential growth of on-
chip transistor capacity, and the challenge is accentuated by the heterogeneity of resources …

Run-time Hardware Reconfiguration of Functional Units to Support Mixed-Critical Applications

RS Ferreira, J Nolte, F Vargas… - 2020 IEEE Latin …, 2020 - ieeexplore.ieee.org
System reconfiguration of hardware resources has been done in multiple system domains.
Such systems are usually found in the context of FPGAs, where reconfiguration is done …

Hasti: hardware‐assisted functional testing of embedded processors in idle times

A Kamran - IET Computers & Digital Techniques, 2019 - Wiley Online Library
In the past decades, software‐based self‐testing (SBST) which is testing of a processing
core using its native instructions has attracted much attention. However, efficient SBST of a …

Exploring system availability during software-based self-testing of multi-core cpus

MA Skitsas, CA Nicopoulos, MK Michael - Journal of Electronic Testing, 2018 - Springer
As technology scales, the increased vulnerability of modern systems due to unreliable
components becomes a major problem in the era of multi-/many-core architectures …

A processor and cache online self-testing methodology for OS-managed platform

CW Lin, CH Chen - IEEE Transactions on Very Large Scale …, 2017 - ieeexplore.ieee.org
Software-based self-test (SBST) is an effective method to detect operational faults of a
processor system. We propose an architectural approach to support high fault-coverage …

Run-time redundancy management of processor functional units for mixed-critical scenarios

R Segabinazzi Ferreira - 2022 - opus4.kobv.de
Since electronics started to scale down, a growing concern about the reliability of these
electronic devices has emerged. At the same time, the increased demand for high …