Content addressable memory array programmed to perform logic operations
BACKGROUND The present invention relates to memory devices, and more specifically, to
content addressable memory devices. Random access memory (RAM) associates data with …
content addressable memory devices. Random access memory (RAM) associates data with …
Three-dimensional two-terminal memory with enhanced electric field and segmented interconnects
Providing for three-dimensional memory cells having enhanced electric field characteristics
and/or memory cells located at broken interconnects is described herein. By way of …
and/or memory cells located at broken interconnects is described herein. By way of …
Integrated piezoelectric micromechanical ultrasonic transducer pixel and array
HV Panchawagh, S Ganti, KD Djordjev… - US Patent …, 2019 - Google Patents
An ultrasonic sensor pixel includes a substrate, a piezoelectric micromechanical ultrasonic
transducer (PMUT) and a sensor pixel circuit. The PMUT includes a piezoelectric layer stack …
transducer (PMUT) and a sensor pixel circuit. The PMUT includes a piezoelectric layer stack …
Three-port piezoelectric ultrasonic transducer
A piezoelectric micromechanical ultrasonic transducer (PMUT) includes a diaphragm
disposed over a cavity, the diaphragm including a piezoelectric layer stack including a …
disposed over a cavity, the diaphragm including a piezoelectric layer stack including a …
Two terminal resistive switching device structure and method of fabricating
SH Jo, SB Herner - US Patent 9,012,307, 2015 - Google Patents
(57) ABSTRACT A method of forming a two terminal device. The method includes forming a
first dielectric material overlying a Surface region of a Substrate. A bottom wiring material is …
first dielectric material overlying a Surface region of a Substrate. A bottom wiring material is …
Field programmable gate array utilizing two-terminal non-volatile memory
M Asnaashari, H Nazarian, S Nguyen - US Patent 10,056,907, 2018 - Google Patents
A method for an FPGA includes coupling a first electrode of a first resistive element to a first
input voltage, coupling a second electrode of a second resistive element to a second input …
input voltage, coupling a second electrode of a second resistive element to a second input …
Three-dimensional oblique two-terminal memory with enhanced electric field
SH Jo, J Bettinger, LIU Xianliang - US Patent 9,627,443, 2017 - Google Patents
Related US Application Data is a continuation-in-part of application No. 13/525, 096, filed on
Jun. 15, 2012, now Pat. No. 9,058,865, said application No. 14/027,045 is a continuation-in …
Jun. 15, 2012, now Pat. No. 9,058,865, said application No. 14/027,045 is a continuation-in …
Reduced diffusion in metal electrode for two-terminal memory
SP Maxwell, SH Jo - US Patent 9,685,608, 2017 - Google Patents
Providing for two-terminal memory that mitigates diffusion of external material therein is
described herein. In some embodiments, a two-terminal memory cell can comprise an …
described herein. In some embodiments, a two-terminal memory cell can comprise an …
Method of operating a resistive memory device with a ramp-up/ramp-down program/erase pulse
D Kamalanathan, FS Koushan, JPS Echeverry… - US Patent …, 2015 - Google Patents
In one embodiment, a method of operating a resistive Switch ing device includes applying a
signal comprising a pulse on a first terminal of a two terminal resistive switching device …
signal comprising a pulse on a first terminal of a two terminal resistive switching device …
Seed layer for a p+ silicon germanium material for a non-volatile memory device and method
MH Clark, SB Herner - US Patent 9,252,191, 2016 - Google Patents
5,538,564 A 7, 1996 Kaschmitter 7,897.953 B2 3/2011 Liu 5.541, 869. A 7, 1996 Rose et al.
7,898,838 B2 3/2011 Chen et al. 5594, 363 A 1/1997 Freeman et al. 7920, 412 B2 4/2011 …
7,898,838 B2 3/2011 Chen et al. 5594, 363 A 1/1997 Freeman et al. 7920, 412 B2 4/2011 …