A survey of optimization techniques for thermal-aware 3D processors

K Cao, J Zhou, T Wei, M Chen, S Hu, K Li - Journal of Systems Architecture, 2019 - Elsevier
Interconnect scaling has become a major design challenge for traditional planar (2D)
integrated circuits (ICs). Three-dimensional (3D) IC that stacks multiple device layers …

A survey on mapping and scheduling techniques for 3D Network-on-chip

SP Kaur, M Ghose, A Pathak, R Patole - Journal of Systems Architecture, 2024 - Elsevier
Abstract Network-on-chips (NoCs) have been widely employed in the design of
multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs …

Minimizing temperature and energy of real-time applications with precedence constraints on heterogeneous MPSoC systems

T Li, T Zhang, G Yu, J Song, J Fan - Journal of Systems Architecture, 2019 - Elsevier
The energy issue of real-time applications with precedence-constrained tasks on
heterogeneous systems has been studied recently. With the strikingly increasing power …

3D-DNaPE: Dynamic Neighbor-Aware Performance Enhancement for Thermally Constrained 3D Many-Core Systems

MS Mohammed, A Al-Dhamari, M Hamdan… - IEEE …, 2023 - ieeexplore.ieee.org
The continuous scaling of silicon technology has enabled many-core systems to become
ubiquitous, offering enormous computational power for various applications spanning from …

Thermal-throttling server: A thermal-aware real-time task scheduling framework for three-dimensional multicore chips

TH Tsai, YS Chen - Journal of Systems and Software, 2016 - Elsevier
Abstract Three-dimensional (3D) multicore chips have been recently developed to deal with
the power consumption and interconnection delay problems of embedded systems; …

Runtime performance optimization of 3-D microprocessors in dark silicon

H Wang, W Li, W Qi, D Tang, L Huang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Because the increasing power density is limited by the thermal constraint, multi-core
integrated systems have stepped into the dark silicon era recently, meaning not all parts of …

Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics

Z Zhu, V Chaturvedi, AK Singh… - 2017 22nd Asia and …, 2017 - ieeexplore.ieee.org
In this paper, we propose a two-stage thermal-aware task scheduling policy which exploits
the application and system architecture characteristics to decouple the mapping of task …

TB-NUCA: A Temperature-Balanced 3D NUCA Based on Bayesian Optimization

H Liu, Y Zhao, X Chen, C Li, J Lu - Electronics, 2022 - mdpi.com
Three-dimensional network-on-chip (NoC) is the primary interconnection method for 3D-
stacked multicore processors due to their excellent scalability and interconnect flexibility …

Augmented cross-entropy-based joint temperature optimization of real-time 3-D MPSoC systems

Y Cui, K Cao, L Li, J Zhou, T Wei… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
3-D multiprocessor system-on-chip (MPSoC) systems can offer higher integration density,
lower interaction cost, better bandwidth, and greater performance. However, vertically …

Real-time scheduling of embedded applications on multi-core platforms

M Fan - 2014 - digitalcommons.fiu.edu
For the past several decades, we have experienced the tremendous growth, in both scale
and scope, of real-time embedded systems, thanks largely to the advances in IC technology …