We present SonicBOOM, the third generation of the Berkeley Outof-Order Machine (BOOM).
SonicBOOM is an open-source RTL implementation of a RISC-V superscalar out-of-order …

The numerous emerging implementations of RISC-V processors and frameworks underline
the success of this Instruction Set Architecture (ISA) specification. The free and open source …

Radiation can affect the correct behavior of an electronic device. Hence, the
microprocessors used for space missions need to be protected against fault. TMR (Triple …

In modern real-time heterogeneous System-on-Chips (SoCs), ensuring the predictability of
interconnects is becoming increasingly important. Most of the existing interconnects are …

Memories play an essential role in computer systems as they store and retrieve data that
may include instructions required for system operation. In the case of an assembler, the …

For safety-critical| computer systems, time-predictability and performance are usually
required simultaneously in I/O virtualization. However, both requirements are challenging to …

Simodense is a high-performance open-source RISC-V (RV32IM) softcore, optimised for
exploring custom SIMD instructions. In order to maximise SIMD instruction performance, the …

RISC-V is a RISC based open and loyalty free instruction set architecture which has been
developed since 2010, and can be used for cost-effective soft processors on FPGAs. The …

Various verification methods have been proposed for bug detection in central processing
unit (CPU) designs, yet their effectiveness remains insufficient. We have observed that such …

Out-of-order superscalar processors are currently the only architecture that speeds up
irregular programs, but they suffer from poor power efficiency. To tackle this issue, we …