[图书][B] Memory systems: cache, DRAM, disk

B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stopping your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …

Scaling of stack effect and its application for leakage reduction

S Narendra, V De, D Antoniadis… - Proceedings of the …, 2001 - dl.acm.org
Technology scaling demands a decrease in both Vdd and Vt to sustain historical delay
reduction, while restraining active power dissipation. Scaling of Vt however leads to …

Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

Z Chen, M Johnson, L Wei, K Roy - Proceedings of the 1998 …, 1998 - dl.acm.org
Low supply voltage requires the device threshold to be reduced in order to maintain
performance. Due to the exponential relationship between leakage current and threshold …

LECTOR: a technique for leakage reduction in CMOS circuits

N Hanchate, N Ranganathan - IEEE Transactions on Very …, 2004 - ieeexplore.ieee.org
In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to
increase in subthreshold leakage current and hence static power dissipation. We propose a …

Leakage current reduction in CMOS VLSI circuits by input vector control

A Abdollahi, F Fallah, M Pedram - IEEE Transactions on Very …, 2004 - ieeexplore.ieee.org
The first part of this paper describes two runtime mechanisms for reducing the leakage
current of a CMOS circuit. In both cases, it is assumed that the system or environment …

[PDF][PDF] Leakage control with efficient use of transistor stacks in single threshold CMOS

MC Johnson, D Somasekhar, K Roy - … of the 36th annual ACM/IEEE …, 1999 - dl.acm.org
The state dependence of leakage can be exploited to obtain modest leakage savings in
CMOS circuits. However, one can modify circuits considering state dependence and achieve …

[图书][B] Statistical analysis and optimization for VLSI: Timing and power

A Srivastava, D Sylvester, D Blaauw - 2006 - books.google.com
Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book
on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest …

[图书][B] Design for manufacturability and statistical design: a constructive approach

M Orshansky, S Nassif, D Boning - 2007 - books.google.com
Design for Manufacturability and Statistical Design: A Constructive Approach provides a
thorough treatment of the causes of variability, methods for statistical data characterization …

Power grid analysis benchmarks

SR Nassif - 2008 Asia and South Pacific Design Automation …, 2008 - ieeexplore.ieee.org
Benchmarks are an immensely useful tool in performing research since they allow for rapid
and clear comparison between different approaches to solving CAD problems. Recent …

Ultralow-voltage, minimum-energy CMOS

S Hanson, B Zhai, K Bernstein… - IBM journal of …, 2006 - ieeexplore.ieee.org
Energy efficiency has become a ubiquitous design requirement for digital circuits.
Aggressive supply-voltage scaling has emerged as the most effective way to reduce energy …