Chip and Package-Scale Interconnects for General-Purpose, Domain-Specific and Quantum Computing Systems-Overview, Challenges and Opportunities
The anticipated end of Moore's law, coupled with the breakdown of Dennard scaling,
compelled everyone to conceive forthcoming computing systems once transistors reach their …
compelled everyone to conceive forthcoming computing systems once transistors reach their …
Problems and challenges of emerging technology networks− on− chip: A review
AB Achballah, SB Othman, SB Saoud - Microprocessors and Microsystems, 2017 - Elsevier
Abstract Networks− on− chip (NoC) are an alternative to alleviate the problems of legacy
interconnect fabrics. However, many emerging technology NoC are developed and are now …
interconnect fabrics. However, many emerging technology NoC are developed and are now …
ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform
Abstract Network-on-chip (NoC) is an emerging interconnect infrastructure to address the
scalability limitation of conventional shared bus architecture for many-core system-on-chip …
scalability limitation of conventional shared bus architecture for many-core system-on-chip …
From latency-insensitive design to communication-based system-level design
LP Carloni - Proceedings of the IEEE, 2015 - ieeexplore.ieee.org
By the end of the 20th century, the continuous progress of the semiconductor industry
brought a major transformation in the design of integrated circuits: as the speed of global …
brought a major transformation in the design of integrated circuits: as the speed of global …
An approximate communication framework for network-on-chips
Y Chen, A Louri - IEEE Transactions on Parallel and Distributed …, 2020 - ieeexplore.ieee.org
Current multi-/many-core systems spend large amounts of time and power transmitting data
across on-chip interconnects. This problem is aggravated when data-intensive applications …
across on-chip interconnects. This problem is aggravated when data-intensive applications …
Achieving high-performance on-chip networks with shared-buffer routers
On-chip routers typically have buffers dedicated to their input or output ports for temporarily
storing packets in case contention occurs on output physical channels. Buffers …
storing packets in case contention occurs on output physical channels. Buffers …
[PDF][PDF] A survey of network-on-chip tools
AB Achballah, SB Saoud - … Journal of Advanced Computer Science and …, 2013 - Citeseer
Nowadays System-On-Chips (SoCs) have evolved considerably in term of performances,
reliability and integration capacity. The last advantage has induced the growth of the number …
reliability and integration capacity. The last advantage has induced the growth of the number …
The fast evolving landscape of on-chip communication: Selected future challenges and research avenues
D Bertozzi, G Dimitrakopoulos, J Flich… - Design Automation for …, 2015 - Springer
As multi-core systems transition to the many-core realm, the pressure on the interconnection
network is substantially elevated. The Network-on-Chip (NoC) is expected to undertake the …
network is substantially elevated. The Network-on-Chip (NoC) is expected to undertake the …
Deep reinforcement learning enabled self-configurable networks-on-chip for high-performance and energy-efficient computing systems
MF Reza - IEEE Access, 2022 - ieeexplore.ieee.org
Network-on-Chips (NoC) has been the superior interconnect fabric for multi/many-core on-
chip systems because of its scalability and parallelism. On-chip network resources can be …
chip systems because of its scalability and parallelism. On-chip network resources can be …
Energy-efficient and high-performance NoC architecture and mapping solution for deep neural networks
With the advancement and miniaturization of transistor technology, hundreds of cores can
be integrated on a single chip. Network-on-Chips (NoCs) are the de facto on-chip …
be integrated on a single chip. Network-on-Chips (NoCs) are the de facto on-chip …