Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

I Ferain, CA Colinge, JP Colinge - Nature, 2011 - nature.com
For more than four decades, transistors have been shrinking exponentially in size, and
therefore the number of transistors in a single microelectronic chip has been increasing …

Vertical silicon nanowire field effect transistors with nanoscale gate-all-around

Y Guerfi, G Larrieu - Nanoscale research letters, 2016 - Springer
Nanowires are considered building blocks for the ultimate scaling of MOS transistors,
capable of pushing devices until the most extreme boundaries of miniaturization thanks to …

Overview and status of bottom-up silicon nanowire electronics

A Fasoli, WI Milne - Materials science in semiconductor processing, 2012 - Elsevier
This review summarises the recent advances in the field of silicon nanowire electronics from
bottom-up assembled materials. The aim is to draw a comparison between bottom-up and …

Sub-10 nm junctionless carbon nanotube field-effect transistors with improved performance

K Tamersit - AEU-International Journal of Electronics and …, 2020 - Elsevier
Carbon nanotube field-effect transistors (CNTFETs) and their growing applications are
becoming part of modern nanoelectronics, which is in urgent need for high-performance …

The junctionless transistor

JP Colinge - Emerging devices for low-power and high …, 2018 - taylorfrancis.com
The junctionless transistor consists of a piece of uniformly doped semiconductor with a gate
placed between the source and drain contacts and is, therefore, the simplest transistor …

Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs

N Kumar, V Purwar, H Awasthi, R Gupta, K Singh… - Microelectronics …, 2021 - Elsevier
The present article deals with the analytical modeling of threshold voltage of an ultra-thin
nanotube Junctionless double-gate-all-around (NJL-DGAA) metal-oxide-semiconductor field …

Analytical models for electric potential, threshold voltage, and subthreshold swing of junctionless surrounding-gate transistors

G Hu, P Xiang, Z Ding, R Liu, L Wang… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Analytical models for electric potential, threshold voltage, and subthreshold swing of the
junctionless surrounding-gate field-effect transistors are presented. Poisson equation is …

Experimental demonstration of ultrashort-channel (3 nm) junctionless FETs utilizing atomically sharp V-grooves on SOI

S Migita, Y Morita, T Matsukawa… - IEEE Transactions …, 2014 - ieeexplore.ieee.org
Ultrashort-channel junctionless FETs (JL-FETs) were fabricated on silicon-on-insulator
substrates utilizing atomically sharp V-shaped grooves produced by anisotropic wet etching …

[HTML][HTML] A two-dimensional analytical model for short channel junctionless double-gate MOSFETs

C Jiang, R Liang, J Wang, J Xu - AIP Advances, 2015 - pubs.aip.org
A physics-based analytical model of electrostatic potential for short-channel junctionless
double-gate MOSFETs (JLDGMTs) operated in the subthreshold regime is proposed, in …

A computational study of short-channel effects in double-gate junctionless graphene nanoribbon field-effect transistors

K Tamersit - Journal of Computational Electronics, 2019 - Springer
As the channel length shrinks below the 10-nm regime, emerging materials, junctionless
technology, and multiple-gate geometries provide an excellent combination to continue …